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| Patent # | Description |
|---|---|
| US-9,431,120 |
Memory die and method for efficient use of data latches in serving mixed
traffic loads A memory die is provided comprising a non-volatile memory organized in physical pages, a transfer data latch in communication with the non-volatile memory, at... |
| US-9,431,119 |
Adjustable read time for memory Apparatuses, systems, methods, and computer program products are disclosed for controlling a read time of an electronic memory device. A method includes reading... |
| US-9,431,118 |
System, method and computer program product for processing read threshold
information and for reading a flash... A method comprising: generating or receiving read threshold information indicative of multiple read thresholds values that were applied when reading multiple... |
| US-9,431,117 |
Memory system and read reclaim method thereof A memory system includes a nonvolatile memory device including a first memory area formed of memory blocks which store n-bit data per cell and a second memory... |
| US-9,431,116 |
Configuration parameter management using a configuration tool Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. An initialization module is configured to... |
| US-9,431,115 |
Erase system and method of nonvolatile memory device An erase system and method of a nonvolatile memory device includes supplying an erase voltage to a plurality of memory cells of a nonvolatile memory, performing... |
| US-9,431,114 |
Semiconductor device and method of operating the same using state code A method of operating a semiconductor device includes dividing an operation of the semiconductor device into a plurality of periods, and determining a plurality... |
| US-9,431,113 |
Data storage system with dynamic erase block grouping mechanism and method
of operation thereof Systems, methods and/or devices are used to enable dynamic erase block grouping. In one aspect, the method includes (1) maintaining metadata for each erase... |
| US-9,431,112 |
Semiconductor memory device including strings including memory cell
transistors A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each... |
| US-9,431,111 |
One time programming memory cell, array structure and operating method
thereof A one time programming memory cell includes a transistor, a first varactor, and a second varactor. The transistor has a gate terminal, a source terminal and a... |
| US-9,431,110 |
Column address decoding Methods, memories and systems to access a memory may include generating an address during a first time period, decoding the address during the first time... |
| US-9,431,109 |
Parallel bitline nonvolatile memory employing channel-based processing
technology Various aspects provide for a new combination of non-volatile memory architecture and memory processing technology. A memory cell has a gate node, a source node... |
| US-9,431,108 |
Integrated structure comprising neighboring transistors An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor... |
| US-9,431,107 |
Memory devices and methods of manufacture thereof Memory devices and methods of manufacture thereof are disclosed. In one embodiment, a memory device includes a transistor having a gate disposed over a... |
| US-9,431,106 |
Ternary content addressable memory (TCAM) with magnetic tunnel junction
(MTJ) devices A ternary content addressable memory (TCAM) cell is coupled to a first word line and a first match line and includes a first data storage portion coupled to a... |
| US-9,431,105 |
Method and apparatus for memory access management In an embodiment, a method for managing access to memory includes receiving requests for access to a memory from one or more devices, each particular request... |
| US-9,431,104 |
Reconfigurable circuit and method of programming the same A reconfigurable circuit according to an embodiment includes: first wiring lines; second wiring lines crossing the first wiring lines; resistive change elements... |
| US-9,431,103 |
Apparatus to store data and methods to read memory cells Apparatus to store data and methods to read memory cells are disclosed. A disclosed example method involves, during a read cycle of a memory cell, applying a... |
| US-9,431,102 |
Apparatus and method for reading a phase-change memory cell An apparatus and a method of reading a phase-change memory cell are described. A circuit includes a current ramp circuit. A current forcing module is coupled to... |
| US-9,431,101 |
Resistive devices and methods of operation thereof In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a... |
| US-9,431,100 |
Device and method for storing or switching A method for storing or switching. The method comprises: arranging a first layer including a first molecular network having a first 2D lattice structure and a... |
| US-9,431,099 |
Neuromorphic device with excitatory and inhibitory functionalities Provided is a neuromorphic device including first and second lower electrodes formed on a substrate to be electrically separated, first and second lower... |
| US-9,431,098 |
Structure for reducing pre-charge voltage for static random-access memory
arrays A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read... |
| US-9,431,097 |
Volatile/non-volatile SRAM device A method of operation of a static random access memory (SRAM) storage element includes programming a value to the SRAM storage element prior to a power-down... |
| US-9,431,096 |
Hierarchical negative bitline boost write assist for SRAM memory devices A memory device having a plurality of banks of memory cells may be provided. Each memory cells may be interconnected via a local write bit-line and a... |
| US-9,431,095 |
High-density integrated circuit memory A memory circuit includes an input stage having N input ports and N output ports, wherein N is an integer greater than one. The memory circuit further includes... |
| US-9,431,094 |
Input buffer Apparatuses including a data input circuit of a semiconductor device are described. An example apparatus includes a first transistor that receives a reference... |
| US-9,431,093 |
Semiconductor device and method of driving the same A semiconductor device includes: a control block suitable for generating a clock control signal in response to a write training signal and a write-related... |
| US-9,431,092 |
Memory device and memory system including the same A memory device includes a plurality of memory blocks; an address counter suitable for generating a counted address which is used for a normal refresh operation... |
| US-9,431,091 |
Multiple gating modes and half-frequency dynamic calibration for DDR
memory controllers Circuits and methods are described for a DDR memory controller where two different DQS gating modes are utilized. These gating modes together ensure that the... |
| US-9,431,090 |
Memory systems and methods for dynamically phase adjusting a write strobe
and data to account for receive-clock... A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates... |
| US-9,431,089 |
Optimizing power in a memory device Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal... |
| US-9,431,088 |
Package including a plurality of stacked semiconductor devices including a
capacitance enhanced through via and... A plurality of semiconductor memory devices on a multi-chip package is disclosed. Each semiconductor device may include a plurality of through vias and a... |
| US-9,431,087 |
Multi-channel self refresh device A multi-channel self refresh device may include period generation circuit configured to output a self refresh pulse signal having a predetermined time period in... |
| US-9,431,086 |
Memory circuit and refresh method thereof A memory circuit is provided. The memory circuit includes a memory array, a plurality of word lines and a memory controller. The memory array has a plurality of... |
| US-9,431,085 |
Most activated memory portion handling Activation of portions of a memory is tracked to allow an affected portion of the memory to be refreshed before it is corrupted by multiple activations. An... |
| US-9,431,084 |
Determining and storing bit error rate relationships in spin transfer
torque magnetoresistive random-access... Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method may include... |
| US-9,431,083 |
Nonvolatile memory device and storage device having the same A nonvolatile memory device according to the inventive concepts performs a read operation from a true cell storing data and complementary cell storing... |
| US-9,431,082 |
Magneto-electronic component, and method for the production thereof A magneto-electronic component, having one or more elongate elements of a magnetic material, electrically conductive contacts, at least one insulating thin... |
| US-9,431,081 |
Memory device A memory device includes a plurality of normal word lines arranged at a first distance from each other, a redundant word line arranged at a second distance,... |
| US-9,431,080 |
Shared tracking circuit A system includes a first plurality of memory macros and a first tracking circuit associated with a memory macro of the first plurality of memory macros. Each... |
| US-9,431,079 |
Systems and methods of memory and memory operation involving input
latching, self-timing and/or other features Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include... |
| US-9,431,078 |
Semiconductor storage device and control method thereof According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips... |
| US-9,431,077 |
Dual host embedded shared device controller Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific... |
| US-9,431,076 |
Memory system, semiconductor device and methods of operating the same A memory system, a semiconductor memory device and methods of operating the same may perform a read operation on the basis of flag data stored in a flag... |
| US-9,431,075 |
Memory macro configuration and method A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is... |
| US-9,431,074 |
Shiftable memory supporting bimodal storage A shiftable memory supporting bimodal data storage includes a memory having built-in shifting capability to shift a contiguous subset of data stored in the... |
| US-9,431,073 |
Low power memory device A memory device includes a memory cell unit, a bit line unit and a buffering unit. The memory cell unit includes a plurality of memory cell groups. Each memory... |
| US-9,431,072 |
On-the-fly trimmable sense amplifier A trimmable sense amplifier for use in a memory device is disclosed. |
| US-9,431,071 |
Bit-line sense amplifier capable of compensating mismatch between
transistors, and semiconductor memory device... A bit-line sense amplifier may include a pull-up driving circuit, a pull-down driving circuit and a latch-type sense amplifier. The pull-up driving circuit... |
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