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Patent # Description
US-9,430,415 Concurrent dumping of large address space
A method for managing concurrent system dumps of address spaces of memory of a computing system. The method comprises analyzing address space of memory to...
US-9,430,414 Bus independent platform for sensor hub peripherals to provide coalescing of multiple reports
A disclosed computer system includes a processor, an I/O hub including a first host bus interface to communicate via a first transport bus, and a sensor hub....
US-9,430,413 Detecting state loss on a device
This document describes techniques for detecting state loss on a device. These techniques permit a computer connected to a device to forgo, in many cases,...
US-9,430,412 NVM express controller for remote access of memory and I/O over Ethernet-type networks
A method and system for enabling Non-Volatile Memory express (NVMe) for accessing remote solid state drives (SSDs) (or other types of remote non-volatile...
US-9,430,411 Method and system for communicating with non-volatile memory
Apparatus and methods implemented therein are disclosed for communicating with flash memories. The apparatus comprises a flash interface module and a processor...
US-9,430,410 Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
A method for supporting a plurality of load accesses is disclosed. A plurality of requests to access a data cache is accessed, and in response, a tag memory is...
US-9,430,409 Memory protection
An integrated-circuit device (1) comprises a processor (7), memory (13) for storing executable code, and memory protection logic (9). The memory protection...
US-9,430,408 Apparatuses for securing program code stored in a non-volatile memory
An embodiment of an apparatus for securing program code stored in a non-volatile memory is introduced. A non-volatile memory contains a first region and a...
US-9,430,407 Method and system for secure storage and retrieval of machine state
A machine state vector is received at a memory. The machine state vector has a machine state and a machine identifier. Write access qualification is met if the...
US-9,430,406 System for generating a cryptographic key from a memory used as a physically unclonable function
An electronic system 100 for generating a cryptographic key, the system comprising a memory 110 used as a physically unclonable function, the memory being...
US-9,430,405 Encrypted purging of data from content node storage
Described herein are methods, systems, and software for encrypting and erasing data objects in a content node. In one example, a method of operating a content...
US-9,430,404 Thinly provisioned flash cache with shared storage pool
For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and...
US-9,430,403 Optimizing system memory usage
A computer determines whether a page boundary of a page has been crossed by a function. Based on the computer determining that the page boundary has been...
US-9,430,402 System and method for providing stealth memory
The described implementations relate to computer memory. One implementation provides a technique that can include providing stealth memory to an application....
US-9,430,401 Implementing paging optimization to avoid populate on page fault during an IO read
A method and system for implementing paging optimization to avoid populate on page fault during an Input Output (IO) read. A size of the IO read is evaluated....
US-9,430,400 Migration directives in a unified virtual memory system architecture
One embodiment of the present invention sets forth a computer-implemented method for altering migration rules for a unified virtual memory system. The method...
US-9,430,399 Multi-core online patching method and apparatus
A multi-core online patching method and an apparatus for mapping patch data to a patch area of a shared memory are disclosed. A method of the embodiment of the...
US-9,430,398 Adjunct component to provide full virtualization using paravirtualized hypervisors
A system configuration is provided with a paravirtualizing hypervisor that supports different types of guests, including those that use a single level of...
US-9,430,397 Processor and control method thereof
A processor includes a directory cache provided with a data cache, a memory directory to hold directory information, to hold dirty information indicating if...
US-9,430,396 Updating persistent data in persistent memory-based storage
A processor includes a processing core to execute an application including instructions encoding a transaction with a persistent memory via a volatile cache...
US-9,430,395 Grouping and dispatching scans in cache
A method, system, and computer program product for grouping and dispatching scans in a cache directory of a processing environment is provided. A plurality of...
US-9,430,394 Storage system having data storage lines with different data storage line sizes
A storage system includes a data storage device having a plurality of data storage lines, a tag storage device having a plurality of address tags each...
US-9,430,393 System and method for managing cache
A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter...
US-9,430,392 Supporting large pages in hardware prefetchers
Technologies for supporting large pages in hardware prefetchers are described. A processor includes a processor core comprising a pipeline, cache memory and a...
US-9,430,391 Managing coherent memory between an accelerated processing device and a central processing unit
Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems....
US-9,430,390 Core in-memory space and object management architecture in a traditional RDBMS supporting DW and OLTP applications
Techniques are provided for managing in-memory space and objects. In one embodiment, a set of in-memory objects are maintained within an area in volatile memory...
US-9,430,389 Prefetch with request for ownership without data
A method performed by a processor is described. The method includes executing an instruction. The instruction has an address as an operand. The executing of the...
US-9,430,388 Scheduler, multi-core processor system, and scheduling method
A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core...
US-9,430,387 Decoupling data and metadata in hierarchical cache system
A coordinating node creates virtual storage from a hierarchy of local and remote cache storage resources by maintaining global logical block address (LBA)...
US-9,430,386 Multi-leveled cache management in a hybrid storage system
A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The...
US-9,430,385 Moveable locked lines in a multi-level cache
A processor includes a multi-level cache hierarchy where a lock property is associated with a cache line. The cache line retains the lock property and may move...
US-9,430,384 Instructions and logic to provide advanced paging capabilities for secure enclave page caches
Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a...
US-9,430,383 Fast data initialization
A method and system for fast file initialization is provided. An initialization request to create or extend a file is received. The initialization request...
US-9,430,382 Logging addresses of high-availability data
A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a...
US-9,430,381 Processing order with integer inputs and floating point inputs
A graphics processing unit 2 includes a texture pipeline 6 which performs filter operations upon texture values. If the texture values are integer texture...
US-9,430,380 Managing memory transactions in a distributed shared memory system supporting caching above a point of coherency
In response to execution in a memory transaction of a transactional load instruction that speculatively binds to a value held in a store-through upper level...
US-9,430,379 Dynamic random access memory controller
A memory controller comprises a memory controller core that receives packets of data and generates memory transactions for each of the packets of data. A memory...
US-9,430,378 Differential delay compensation
In one embodiment, a method includes receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of...
US-9,430,377 Methods and systems for preserving blocks that are neither obsolete nor cold
A storage device made up of multiple storage media is configured such that one such media serves as a cache for data stored on another of such media. The device...
US-9,430,376 Priority-based garbage collection for data storage systems
Priority-based garbage collection utilizes attributes of data stored in the non-volatile memory array in order to improve efficiency of garbage collection and...
US-9,430,375 Techniques for storing data in bandwidth optimized or coding rate optimized code words based on data access...
A technique for operating a data storage system that includes a non-volatile memory array controlled by a controller includes storing, in the non-volatile...
US-9,430,374 Non-volatile memory system and host configured to communicate with the same
A nonvolatile memory system includes a memory controller for copying a mapping data group including logical-physical address mapping information regarding user...
US-9,430,373 Apparatus including memory channel control circuit and related methods for relaying commands to logical units
Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can...
US-9,430,372 Apparatus, method and system that stores bios in non-volatile random access memory
A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in the platform storage hierarchy. The NVRAM is ...
US-9,430,370 Universal protocol for power tools
A system and method for communicating with power tools using a universal protocol. The universal protocol may be implemented using a universal core module that...
US-9,430,369 Memory-network processor with programmable optimizations
Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated...
US-9,430,368 System and method for caching data
A method, computer program product, and computing system for processing a read request for a piece of content stored within a storage system. If it is...
US-9,430,367 Systems and methods for active raid
A first RAID module is added to a first RAID controller and a second RAID module is added to a second RAID controller. An array of physical disks is partitioned...
US-9,430,366 Distributed logical track layout in optical storage tape
An optical data storage tape includes more than one segment, with each segment divided into multiple zones, which include multiple data tracks. The layout of...
US-9,430,365 Managing high speed memory
A mechanism is provided for managing a high speed memory. An index entry indicates a storage unit in the high speed memory. A corresponding non-free index is...
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