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Patent # Description
US-9,438,281 Distortion-compensation device and distortion-compensation method
Disclosed is a distortion compensation apparatus that, by appropriately generating a distortion-compensation coefficient, makes it possible to obtain a desired...
US-9,438,280 In-vehicle communication apparatus
An in-vehicle communication apparatus includes an antenna module, and a wireless communication device physically separated from the antenna module and connected...
US-9,438,279 Wireless device with adaptively-tunable electrically-small antennas
A communication device includes a transmitter (TX), a receiver (RX), one or more adaptively-tunable Electrically-Small Antennas (ESAs), and a control unit. The...
US-9,438,278 Multi-array antenna
In one example, the present disclosure describes an antenna system with at least two linear antenna arrays, each having a plurality of antenna elements. Each...
US-9,438,277 Intermediate frequency spectral placement of bandpass sampled signals
Systems and methods for bandpass sampling of a continuous analog signal according to several embodiments can use a linear relationship between sampling...
US-9,438,276 Method and apparatus for improved performance of iterative decoders on channels with memory
Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the...
US-9,438,275 Transmission apparatus and transmission method
A transmission apparatus includes a mapping unit configured to map a first information associated with detecting an error of a frame into a payload area of the...
US-9,438,274 Data processing block and data storage device including the same
A data processing block that includes a syndrome computation unit suitable for generating odd syndrome values in response to a received codeword, an ELP solver...
US-9,438,273 Method for generating forward error correction packet in multimedia system and method and apparatus for...
A method and apparatus for transmitting a Forward Error Correction (FEC) packet block including a plurality of FEC packets in a multimedia system are provided....
US-9,438,272 Digital phase locked loop circuitry and methods
Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal...
US-9,438,271 Data compression apparatus and method
A data compression apparatus includes a memory and a processor. The processor extracts a second character string as a matching string from a character string...
US-9,438,270 System and method for symbol-space based compression of patterns
A method and system for symbol-space based pattern compression is provided. The method includes identifying a plurality of combinations of symbols in an input...
US-9,438,269 Accelerating codeset conversion in a computing environment
A method for accelerating codeset conversion in a computing environment is provided. The method may include, among other things, receiving one or more requests...
US-9,438,268 Current type D/A converter, delta sigma modulator, and communications device
This D/A converter includes a plurality of D/A converter elements, each comprising current sources configured to supply output currents to output nodes, and...
US-9,438,267 Apparatus and method for digital to analog conversion with current mirror amplification
A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current...
US-9,438,266 Calibrated-output analog-to-digital converter apparatus and methods
A direct current ("DC") calibration reference voltage is applied at an input terminal of an N-level sigma-delta analog-to-digital converter ("ADC"). The ADC...
US-9,438,265 Phase multiplexer
Representative implementations of devices and techniques provide a phase multiplexer that may be associated with at least a communication device. The described...
US-9,438,264 High-speed capacitive digital-to-analog converter and method thereof
A circuit having a capacitor coupling a first circuit node to a second circuit node; a first switch network configured to couple the second circuit node to...
US-9,438,263 Controllable opto-electronic time stretcher, an electro-optical analog to digital converter having non-uniform...
A controllable opto-electronic time stretcher comprising a first wave guide and a second waveguide coupled to the first waveguide along a coupling portion;...
US-9,438,262 Method for testing differential analog-to-digital converter and system therefor
A method and circuit for testing an analog-to-digital converter (ADC) are provided. The method comprises: coupling a single-ended output of an analog signal...
US-9,438,261 Capacitance-to-digital converter and method for providing a digital output signal
A capacitance-to-digital converter (10) comprises a capacitor arrangement (30), a converter (1) that is coupled on its input side to the capacitor arrangement...
US-9,438,260 Semiconductor apparatus and calibration method for analog to digital converter
In a conventional calibration method of an analog to digital converter, it has been difficult to easily derive a plurality of correction coefficients. A...
US-9,438,259 Circuit, an integrated circuit, a transmitter, a receiver, a transceiver, a method for generating a processed...
A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal...
US-9,438,258 Preamplifier, comparator and analog-to-digital converting apparatus including the same
A preamplifier may include: a common active load suitable for providing output impedance; an output polarity changing unit suitable for changing an output...
US-9,438,257 Programmable frequency divider providing output with reduced duty-cycle variations over a range of divide ratios
A programmable frequency divider includes a cascade of frequency-dividing units, each capable of dividing by a first or a second factor. Each unit receives an...
US-9,438,256 Slow to fast clock synchronization
A method and apparatus for synchronizing data transfers from a first clock domain to a second clock domain includes sampling data from circuit included in the...
US-9,438,255 High frequency delay lock loop systems
The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line...
US-9,438,254 Charge pump circuit for a phase locked loop
A phase-locked-loop includes a phase-frequency-detector (PFD) comparing phases of an input signal and feedback signal, and generating therefrom control signals....
US-9,438,253 High speed current mode latch
A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first...
US-9,438,252 Integrated circuits having low power, low interference and programmable delay generators therein and methods of...
A programmable delay generator includes a calibration circuit and a delay line responsive to a calibration control signal generated by the calibration circuit....
US-9,438,251 Clock generating circuit, semiconductor device including the same, and data processing system
A method for generating an internal clock signal by a clock generating circuit, including generating the internal clock signal based on an external clock...
US-9,438,250 Variable rate interpolation with numerically controlled oscillator
A numerically controlled oscillator includes a phase accumulator that outputs a phase word and a clock that periodically outputs a clock signal in accordance...
US-9,438,249 Resonant circuit temperature compensation
Certain aspects of the present disclosure provide methods and apparatus for temperature-dependent adjustment of a resonant circuit, such as that found in a...
US-9,438,248 Low power digital self-gated binary counter
An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The...
US-9,438,247 Apparatus for simplification of input signal
The present disclosure relates to an apparatus for simplification of input signal configured to simplify a process of microprocessor and to enhance a speed by...
US-9,438,246 System and method for qubit readout
A system is provided for multiplexed readout of qubits. The system comprises a plurality of bandpass (BP) filter resonant sections that are each coupled to a...
US-9,438,245 Reducing spontaneous emission in circuit quantum electrodynamics by a combined readout and filter technique
A mechanism relates a superconductor circuit. A .DELTA. circuit includes a first node connecting a Purcell capacitor to a qubit coupling capacitor, a second...
US-9,438,244 Circuits for and methods of controlling power within an integrated circuit
A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated...
US-9,438,243 Programmable logic circuit and nonvolatile FPGA
A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in...
US-9,438,242 Systems and methods for reducing power consumption in semiconductor devices
A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell,...
US-9,438,241 Multipurpose pads used as digital serial and analog interface
An Integrated Circuit, a system, and a method are provided. The disclosed Integrated Circuit may include a plurality of pads exposing internal components of the...
US-9,438,240 Biasing circuit for level shifter with isolation
A circuit includes a biasing circuit that includes a load circuit coupled to a first node. The biasing circuit can output a biasing signal on the first node....
US-9,438,239 Level shifter, DC-DC converter, and level shift method
A level shifter includes: a first cascode portion, including a first transistor of a first conductivity type and a second transistor of a second conductivity...
US-9,438,238 Data processing apparatus, data processing method, and non-transitory computer readable medium having...
Provided is a data processing apparatus including a reconfigurable circuit that has a dynamically-reconfigurable circuit configuration to execute data...
US-9,438,237 High-yielding standard cell library and circuits made therefrom
An improved 20/22 nm standard cell library, as depicted in FIGS. 1-491, achieves surprisingly significant improvements in manufacturing yield, as compared to a...
US-9,438,236 Input/output driver circuit, integrated circuit and method therefor
An input/output (IO) driver circuit is described. The IO buffer driver circuit comprises: at least one input for receiving an input signal and at least one...
US-9,438,235 Gate driver and related circuit buffer
A circuit buffer for outputting a voltage signal having a magnitude greater than a withstand voltage of any circuit element in the circuit buffer includes a...
US-9,438,234 Logic circuit and semiconductor device including logic circuit
A logic circuit that can retain a state even without power supply is provided. The logic circuit includes a first circuit, a pair of retention circuits, and a...
US-9,438,233 Low-power digital logic using a Boolean logic switched inductor-capacitor (SLC) circuit
A low-power digital logic architecture exhibits the same logic and voltage level behavior as standard digital logic. A logic switch and a pair of unidirectional...
US-9,438,232 Buffer circuit for compensating for a mismatch between on-die termination resistors and semiconductor device...
A semiconductor device is provided. The semiconductor device includes a driver circuit, a dummy circuit, and a control unit. The driver circuit is configured to...
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