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Patent # Description
US-9,437,729 High-density power MOSFET with planarized metalization
A method for producing a power MOSFET. The method includes fabricating a plurality of layers of a power MOSFET to produce an upper surface active area and...
US-9,437,728 Semiconductor device
A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction...
US-9,437,727 Semiconductor element including active region, low resistance layer and vertical drift portion
A drain drift portion is a first parallel p-n structure, largely corresponding to a portion directly below a p-type base region forming an active region, formed...
US-9,437,726 Field effect transistor
In a field effect transistor, a carbon concentration in a buffer layer at the side closer to a high resistance layer is not less than ...
US-9,437,725 Semiconductor device and semiconductor substrate
A semiconductor device is provided, which includes a barrier layer 14 formed on a substrate 10 and made of In.sub.xAl.sub.yGa.sub.1-x-yN, a channel layer 16...
US-9,437,724 Semiconductor device and method of manufacturing the semiconductor device
A semiconductor device comprises a substrate, a semiconductor multilayer structure supported by the substrate, and a first nitride transistor provided in a...
US-9,437,723 Manufacturing method of semiconductor device including indium
A semiconductor device includes an electron transit layer configured to be formed on a substrate; an electron supply layer configured to be formed on the...
US-9,437,722 High-voltage vertical power component
A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the...
US-9,437,721 Reverse-conducting IGBT with buffer layer and separation layer for reducing snapback
In the reverse-conducting IGBT according to the present invention, an n-type buffer layer surrounds a p-type collector layer. A p-type separation layer...
US-9,437,720 Semiconductor device
A semiconductor device has emitter regions disposed in at least one cell region in a first inter-trench region, not disposed in a middle inter-trench region,...
US-9,437,719 Method for manufacturing semiconductor device having grooved surface
A technology for reducing contact resistance between a semiconductor substrate and an electrode is provided. A provided method for manufacturing a semiconductor...
US-9,437,718 Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having a wide band gap...
A method of forming a semiconductor structure includes forming a first seed layer, a second seed layer and an intrinsic base spaced apart from each other and...
US-9,437,717 Interface control in a bipolar junction transistor
Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of...
US-9,437,716 Semiconductor device comprising a graphene wire
According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon...
US-9,437,715 Non-volatile memory and manufacturing method thereof
A manufacturing method of a non-volatile memory is provided. A tunneling dielectric layer, a first conductive pattern, and isolation structures are formed on a...
US-9,437,714 Selective gate contact fill metallization
Gate metal is selectively deposited on work function material during formation of a replacement metal gate. The work function material is subjected to a...
US-9,437,713 Devices and methods of forming higher tunability FinFET varactor
Devices and methods for forming semiconductor devices with wider FinFETs for higher tunability of the varactor are provided. One method includes, for instance:...
US-9,437,712 High performance self aligned contacts and method of forming same
A method embodiment includes forming a protective liner over the substrate and forming an inter-layer dielectric over the protective liner. The protective liner...
US-9,437,711 Methods of forming gate structures for semiconductor devices using a replacement gate technique and the...
One method disclosed herein includes, among other things, performing a process operation on an exposed surface of a substrate so as to form an H-terminated...
US-9,437,710 Method for improving transistor performance through reducing the salicide interface resistance
An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a...
US-9,437,709 Semiconductor device and fabrication method thereof
A semiconductor device and a method for fabricating the same are disclosed. In the method, a substrate structure is provided, including a substrate and a...
US-9,437,708 Enhancement mode III-N HEMTs
A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access...
US-9,437,707 Transistors with isolation regions
A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the...
US-9,437,706 Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal...
A microelectronic device may be formed with at least one transistor having a source region and a drain region, wherein an interlayer dielectric layer may be...
US-9,437,705 Method of manufacturing a spacer for dual gate electronic memory cell and associated electronic memory cell
A method of manufacturing a spacer for an electronic memory including a substrate; a first gate structure; a stack including a plurality of layers whereof at...
US-9,437,704 Semiconductor device having electrode made of high work function material, method and apparatus for...
Provided is a semiconductor device including a metal film which can be formed with lower costs but still mange to have a necessary work function and oxidation...
US-9,437,703 Non-volatile memory device including nano floating gate with nanoparticle and method for fabricating the same
A non-volatile memory device includes a floating gate for charging and discharging of charges over a substrate. The floating gate comprises a linker layer...
US-9,437,702 Electronic component manufacturing method and electrode structure
It is an object of the present invention to provide an electronic component manufacturing method, capable of suppressing reduction in a trench opening and...
US-9,437,701 Integrated circuit devices with counter-doped conductive gates
Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a...
US-9,437,700 Semiconductor device
A semiconductor device is provided with a silicon layer, an upper surface side aluminum layer containing silicon and an insulation film. The upper surface side...
US-9,437,699 Method of forming nanowires
According to another embodiment, a semiconductor structure is provided. The structure includes: a substrate; a first nanowire over the substrate; and a second...
US-9,437,698 Semiconductor device including a gate structure wrapped around a fin structure
Methods and structure for a semiconductor device is disclosed, which provides a semiconductor device that includes an integral semiconductor fin structure...
US-9,437,697 Semiconductor device having buried gate structure and method of fabricating the same
A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the...
US-9,437,696 Semiconductor device and method for fabricating the same
A semiconductor device includes a substrate having an element isolation region, a trench formed on the element isolation region, a gate electrode buried in the...
US-9,437,695 Semiconductor device and method of manufacturing the same
According to one embodiment, a semiconductor device includes a semiconductor substrate in which a recess is provided on a back surface thereof, and a shape of...
US-9,437,694 Transistor with a low-k sidewall spacer and method of making same
A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a...
US-9,437,693 Device having a shield plate dopant region and method of manufacturing same
A transistor includes a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield...
US-9,437,692 Production and distribution of dilute species in semiconducting materials
Technologies are described effective to implement systems and methods of producing a material. The methods comprise receiving a tertiary semiconductor sample...
US-9,437,691 Column IV transistors for PMOS integration
Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced...
US-9,437,690 Silicon carbide substrate, semiconductor device, and methods for manufacturing them
A silicon carbide substrate has a first main surface, and a second main surface opposite to the first main surface. A region including at least one main surface...
US-9,437,689 Ga2O3 semiconductor element
A Ga.sub.2O.sub.3 semiconductor element includes: an n-type .beta.-Ga.sub.2O.sub.3 single crystal film, which is formed on a high-resistance...
US-9,437,688 High-quality GaN high-voltage HFETs on silicon
A GaN HFET includes a silicon substrate with an Al.sub.2O.sub.3 layer above the silicon substrate. The Al.sub.2O.sub.3 layer has voids formed therein. A...
US-9,437,687 III-nitride based semiconductor structure
The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor...
US-9,437,686 Gallium nitride devices with discontinuously graded transition layer
The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor...
US-9,437,685 Group III-V device with a selectively reduced impurity concentration
There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body...
US-9,437,684 Method of producing microstructure of nitride semiconductor and photonic crystal prepared according to the method
The method of producing a GaN-based microstructure includes a step of preparing a semiconductor structure provided with a trench formed in a main surface of the...
US-9,437,683 Method and structure for FinFET device
The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with...
US-9,437,682 Semiconductor device and semiconductor device manufacturing method
The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device...
US-9,437,681 Dual channel FinFET CMOS device with common strain-relaxed buffer and method for manufacturing thereof
A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a...
US-9,437,680 Silicon-on-insulator substrates having selectively formed strained and relaxed device regions
A method of forming a semiconductor device substrate includes forming a donor wafer having a surface comprising regions of relaxed silicon and regions of...
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