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Patent # Description
US-9,437,578 Stacked IC control through the use of homogenous region
A package includes a semiconductor chip. The semiconductor chip includes a substrate, a plurality of dielectric layers underlying the substrate, a dielectric...
US-9,437,577 Package on package structure with pillar bump pins and related method thereof
A package on package (POP) structure includes at least a first package and a second package. The first package has a plurality of pillar bump pins. The second...
US-9,437,576 Semiconductor device package and method of manufacturing the same
A semiconductor device package includes a substrate, a first electrical component, a second electrical component, and a conductive frame disposed on a top...
US-9,437,575 Semiconductor device package formed in a chip-on-wafer last process using thin film adhesives
Methods for a semiconductor device package formed in a chip-on-wafer last process using thin film adhesives are disclosed and may include bonding a first...
US-9,437,574 Electronic component package and method for forming same
An electronic component package includes a substrate and dielectric structure. The dielectric structure includes a top surface having a protrusion portion and a...
US-9,437,573 Semiconductor device and method for manufacturing thereof
A semiconductor device which includes a first semiconductor chip 10, a first electrode 12 formed on the first semiconductor chip 10, a second semiconductor chip...
US-9,437,572 Conductive pad structure for hybrid bonding and methods of forming same
A method embodiment includes patterning an opening through a layer at a surface of a device die. The method further includes forming a liner on sidewalls of the...
US-9,437,571 Bonding device
A bonding device includes: a plurality of laser oscillators that oscillate laser beams; a plurality of guide beam parts that guide the laser beams oscillated...
US-9,437,570 Power converter package with an integrated output inductor
In one implementation, a power semiconductor package includes a conductive carrier including a switch node segment and a power output segment. The power...
US-9,437,569 High density substrate routing in BBUL package
Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more...
US-9,437,568 Method for manufacturing semiconductor device having a multilayer interconnection
Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer...
US-9,437,567 Semiconductor devices with ball strength improvement
A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally,...
US-9,437,566 Conductive connections, structures with such connections, and methods of manufacture
In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a...
US-9,437,565 Semiconductor substrate and semiconductor package structure having the same
The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The...
US-9,437,564 Interconnect structure and method of fabricating same
A structure comprises a passivation layer formed over a semiconductor substrate, a connection pad enclosed by the passivation layer, a redistribution layer...
US-9,437,563 Bump structures in semiconductor packages and methods of fabricating the same
The bump structure includes a metal pattern disposed on an electrode pad to have a vertical sidewall and a recessed region surrounded by the vertical sidewalls,...
US-9,437,562 Semiconductor device and manufacturing method of semiconductor device
A manufacturing method of a semiconductor device includes placing a mask having an opening on an external region of a top face of a substrate to locate an end...
US-9,437,561 Semiconductor chip with redundant thru-silicon-vias
A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias...
US-9,437,560 Semiconductor device including landing pad
A semiconductor device includes conductive lines spaced from a substrate, and an insulating spacer structure between the conductive lines and defining a contact...
US-9,437,559 High-frequency module
A high-frequency module includes a laminate, a bottom surface electrode, and internal electrodes that provide grounding. The bottom surface electrode is...
US-9,437,558 High frequency integrated circuit and packaging for same
An integrated circuit can include a group of bond pads alternating between bond pads configured to provide a return path and bond pads configured to provide a...
US-9,437,557 High density three-dimensional integrated capacitors
A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first...
US-9,437,556 Semiconductor device
The reliability of a semiconductor device is improved. Further, miniaturization of the semiconductor device is attained. A sealring is formed in a wiring...
US-9,437,555 Semiconductor device having features to prevent reverse engineering
It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that...
US-9,437,554 Semiconductor package having magnetic substance and related equipment
Provided is a semiconductor device. A semiconductor chip is disposed on a substrate. A first magnetic substance, a second magnetic substance and a third...
US-9,437,553 Electronic device
An electronic device includes a first substrate including a first electrode formed on a surface of the first substrate, an electronic component mounted on...
US-9,437,552 Semiconductor device and method of forming insulating layer around semiconductor die
A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the...
US-9,437,551 Concentric bump design for the alignment in die stacking
An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The...
US-9,437,550 TSV without zero alignment marks
Semiconductor device and method of forming a semiconductor device are disclosed. The method includes providing a substrate. A dielectric layer is formed on the...
US-9,437,549 Method for manufacturing ceramic substrate
A method for manufacturing a ceramic substrate is characterized in using a preformed trench, a patterned protective layer and a sand blasting process to...
US-9,437,548 Chip package and method for manufacturing the same
Various embodiments provide a chip package. The chip package may include a metallic chip carrier; at least one chip carried by the metallic chip carrier;...
US-9,437,547 Through silicon vias
A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate....
US-9,437,546 Method of forming stacked trench contacts and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact...
US-9,437,545 Interconnects having sealing structures to enable selective metal capping layers
Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an...
US-9,437,544 Semiconductor device
A semiconductor device includes a semiconductor chip, a wiring on the chip, an insulating film coating the wiring and having an opening partially exposing the...
US-9,437,543 Composite contact via structure containing an upper portion which fills a cavity within a lower portion
A contact via cavity can be filled with a lower structure and an upper structure. The lower structure can be a conductive structure that is formed by depositing...
US-9,437,542 Chip package structure
A chip package structure is provided. The chip package structure includes a chip, at least one inducting coil, a molding compound and a redistribution circuit...
US-9,437,541 Patterning approach to reduce via to via minimum spacing
A method for patterning vias in a chip comprises forming a photomask layer including a gap on a patterned hardmask layer including a plurality of trenches and...
US-9,437,540 Additional etching to increase via contact area
An integrated circuit structure includes a dielectric layer, and a conductive line in the dielectric layer. The conductive line has a first top surface and a...
US-9,437,539 Dielectric region in a bulk silicon substrate providing a high-Q passive resonator
Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive...
US-9,437,538 Semiconductor device including RDL along sloped side surface of semiconductor die for Z-direction interconnect
A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends...
US-9,437,537 Semiconductor device and method of manufacturing the same
A semiconductor device including conductive lines configured to include first lines extending generally in parallel in a first direction and second lines...
US-9,437,536 Reversed build-up substrate for 2.5D
A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The...
US-9,437,535 Wireless module and production method for wireless module
Provided is a wireless module whose size can be made smaller. The wireless module includes: a first substrate on which an antenna is mounted; a second substrate...
US-9,437,534 Enhanced flip chip structure using copper column interconnect
A flip chip package includes: a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in...
US-9,437,533 Semiconductor memory system
According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer...
US-9,437,532 Substrate for semiconductor package and process for manufacturing
A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward...
US-9,437,530 Combined packaged power semiconductor device
A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal...
US-9,437,529 Chip package structure and manufacturing method thereof
A chip package structure includes a lead frame having first and second patterned metal layers and an insulation layer, a chip, and an encapsulant covering the...
US-9,437,528 Dual-side exposed semiconductor package with ultra-thin die and manufacturing method thereof
A dual-side exposed semiconductor package with ultra-thin die and a manufacturing method are disclosed. A die having a source electrode and a gate electrode at...
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