Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,437,527 Method for manufacturing electrical connections in a semiconductor device and the semiconductor device
A resin casing is insert-molded while clamp protrusions of clamp portions formed in bonding portions of lead terminals are put between an upper mold and a lower...
US-9,437,526 Chip on film package including distributed via plugs
A chip on film (COF) package includes a film substrate, first leads on a first surface of the film substrate, the first leads having a first length, and second...
US-9,437,525 Semiconductor device and manufacturing method thereof
An object is to use an electrode made of a less expensive material than gold (Au). A semiconductor device comprises: a first titanium layer that is formed to...
US-9,437,524 Through-silicon via with sidewall air gap
Embodiments of the present invention provide a novel process integration for air gap formation at the sidewalls for a Through Silicon Via (TSV) structure. The...
US-9,437,523 Two-sided jet impingement assemblies and power electronics modules comprising the same
Power electronics modules having jet impingement assemblies utilized to cool heat generating devices are disclosed. In one embodiment, a jet impingement...
US-9,437,522 Semiconductor device and method for manufacturing semiconductor device
A semiconductor device according to the present invention has a semiconductor module 2; a cooling unit 3, the semiconductor module 2 being joined to an upper...
US-9,437,521 Thermally conductive sheet
A thermally conductive sheet, comprising a curable resin composition, thermally conductive fibers, and thermally conductive particles, wherein the thermally...
US-9,437,520 Semiconductor device including a semiconductor element and a fixed member to which the semiconductor element is...
A semiconductor device includes a semiconductor element having a rectangular shape in a plan view, and a fixed member to which the semiconductor element is...
US-9,437,519 Tim strain mitigation in electronic modules
A lid including a lid body, and a wing portion, the wing portion being disposed on a die side of the lid body such that an edge of the wing portion is flexible...
US-9,437,518 Semiconductor module
A semiconductor module may include a heat-transferring part connecting at least one of a control device, a buffer semiconductor device, and a memory device to a...
US-9,437,517 Semiconductor apparatus including a heat dissipating member
A semiconductor apparatus is provided. The semiconductor apparatus includes: a base having a main surface on which a terminal is disposed; a first semiconductor...
US-9,437,516 Chip-embedded packages with backside die connection
A semiconductor package includes a semiconductor die and a metal clip. In one embodiment, the semiconductor die is embedded in an insulating material and has a...
US-9,437,515 Heat spreading layer with high thermal conductivity
Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat...
US-9,437,514 Semiconductor package with coated side walls and method of manufacture
A semiconductor package including an integrated device, the package having a front side, a back side and side walls linking the front and back sides, wherein...
US-9,437,513 Electrically insulating thermal interface on the discontinuity of an encapsulation structure
Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least...
US-9,437,512 Integrated circuit package structure
An integrated circuit (IC) package structure is provided, including: a first integrated circuit (IC) package, including: a first package substrate, having...
US-9,437,511 Method and structure for wafer-level packaging
A method for wafer-level packaging includes providing a semiconductor wafer having a plurality of semiconductor chips connected by connection stems in the...
US-9,437,510 Opto-electrical device and method for manufacturing thereof
An opto-electrical device is provided that comprises a cover (10), a barrier structure (20), an opto-electrical structure (30) and a plurality of transverse...
US-9,437,509 Package for electronic components suppressing multipactor discharge
A package for electronic components that suppresses multipactor discharge is disclosed. The package includes a metal base and a casing. The metal base provides...
US-9,437,508 Method for manufacturing semiconductor device and semiconductor device
In a method for manufacturing a semiconductor device according to the present invention, as shown in FIG. 2(A), a case (2) including a first terminal (1) is...
US-9,437,507 Method of correcting film thickness measurement value, film thickness corrector and eddy current sensor
The polishing process includes a first state where an eddy current sensor and a polishing target object do not face each other and a second state where the eddy...
US-9,437,506 Semiconductor defect characterization
The defect-containing die identified from an inspection layer analysis subsequent to a manufacturing step for a wafer including a plurality of die and as well...
US-9,437,505 Method of measuring contamination amount of vapor phase growth apparatus, and method of manufacturing epitaxial...
Carry out a vapor etching step of cleaning an inside of a chamber of a vapor phase growth apparatus by vapor etching using HCl gas (S1). Carry out an annealing...
US-9,437,504 Method for the formation of fin structures for FinFET devices
On a first semiconductor material substrate, an overlying sacrificial layer formed of a second semiconductor material is deposited. In a first region, a first...
US-9,437,503 Vertical FETs with variable bottom spacer recess
A method of forming a variable spacer in a vertical transistor device includes forming a first source/drain of a first transistor on a substrate; forming a...
US-9,437,502 Method to form stacked germanium nanowires and stacked III-V nanowires
A first sacrificial gate structure is formed over a first fin stack and a second sacrificial gate structure is formed over a second fin stack. The first and...
US-9,437,501 Stacked nanowire device width adjustment by gas cluster ion beam (GCIB)
A method of making a nanowire device incudes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first...
US-9,437,500 Method of forming supra low threshold devices
A semiconductor device and a method for making the semiconductor device are provided. The semiconductor device includes a non-volatile memory cell having a gate...
US-9,437,499 Semiconductor device including merged-unmerged work function metal and variable fin pitch
A method of varying a threshold voltage of a semiconductor device includes forming plural first semiconductor fins atop a substrate and which are separated from...
US-9,437,498 Method for the formation of different gate metal regions of MOS transistors
A method is for forming at least two different gates metal regions of at least two MOS transistors. The method may include forming a metal layer on a gate...
US-9,437,497 Method of making a FinFET device
A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a...
US-9,437,496 Merged source drain epitaxy
A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes...
US-9,437,495 Mask-less dual silicide process
A method of forming a semiconductor device is provided. The method includes forming a mask layer, such as an oxidized layer, over first source/drain regions in...
US-9,437,494 Semiconductor arrangement and formation thereof
A semiconductor arrangement and method of formation are provided. A method of semiconductor formation includes using a single photoresist to mask off an area...
US-9,437,493 Method of forming a semiconductor die
In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.
US-9,437,492 Substrate for alternative semiconductor die configurations
A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the...
US-9,437,491 Method of forming chip with through silicon via electrode
The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning...
US-9,437,490 Semiconductor device and manufacturing method thereof
A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first...
US-9,437,489 Method of manufacturing a wiring substrate
A method of manufacturing a wiring substrate including a step of forming a through hole that includes forming a first concave portion in a substrate that...
US-9,437,488 Metallization method for semiconductor structures
A method is provided for fabricating a semiconductor device that includes providing a structure with a sacrificial layer having at least one through-hole...
US-9,437,487 Array substrate and fabrication method thereof, and display device
Embodiments of the disclosure disclose an array substrate and a fabrication method thereof, and a display device. The fabrication method of the array substrate...
US-9,437,486 Sputtering target
A sputtering target contains high purity Nb of which Ta content is 3000 ppm or less and oxygen content is 200 ppm or less. Dispersion of the Ta content in all...
US-9,437,485 Method for line stress reduction through dummy shoulder structures
Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to...
US-9,437,484 Etch stop layer in integrated circuits
An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride...
US-9,437,483 Methods for forming etch stop layers, semiconductor devices having the same, and methods for fabricating...
A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the...
US-9,437,482 Semiconductor device and method of forming shielding layer over active surface of semiconductor die
A semiconductor wafer contains a plurality of semiconductor die separated by a non-active area of the semiconductor wafer. A plurality of contact pads is formed...
US-9,437,481 Self-aligned double patterning process for two dimensional patterns
One method includes forming a mandrel element above a hard mask layer, forming first and second spacers on the mandrel element, removing the mandrel element, a...
US-9,437,480 Methods of forming semiconductor structures including tight pitch contacts and lines
Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating...
US-9,437,479 Methods for forming an interconnect pattern on a substrate
Embodiments of methods for forming interconnect patterns on a substrate are provided herein. In some embodiments, a method for forming an interconnect pattern...
US-9,437,478 Chip package and method for forming the same
A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.