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Patent # Description
US-9,437,477 Pattern forming method
In one embodiment, a pattern forming method includes forming a first film on a substrate that includes a convex portion and a concave portion so as to expose an...
US-9,437,476 Method of manufacturing semiconductor device including air gap between patterns
In one embodiment, a method of manufacturing a semiconductor device includes forming a pattern portion and a flat portion on a substrate, the pattern portion...
US-9,437,475 Method for fabricating microelectronic devices with isolation trenches partially formed under active regions
A method of producing a microelectronic device in a substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer,...
US-9,437,474 Method for fabricating microelectronic devices with isolation trenches partially formed under active regions
A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer,...
US-9,437,473 Method for separating at least two substrates along a selected interface
A process for separating at least two substrates comprising at least two separation interfaces along one of the interfaces includes, before inserting a blade...
US-9,437,472 Semiconductor line feature and manufacturing method thereof
Some embodiments of the present disclosure provide a semiconductor structure with a reduced line feature. The semiconductor structure includes a substrate, a...
US-9,437,471 Shallow trench isolations and method of manufacturing the same
A method of manufacturing shallow trench isolations is provided in the present invention, which includes the steps of providing a substrate, performing a zero...
US-9,437,470 Self-aligned trench isolation in integrated circuits
A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An...
US-9,437,469 Inertial wafer centering end effector and transport apparatus
A substrate transport apparatus for a processing tool. The apparatus has a drive section, a movable arm, and an end effector. The arm is operably connected to...
US-9,437,468 Heat assisted handling of highly warped substrates post temporary bonding
A heated non-contact wafer handling gripper may heat a thin device wafer bottom surface having a temporary bonding adhesive residue after debonding of the...
US-9,437,467 Substrate handler
A loadport for handling film frames is disclosed. The loadport is modular and substantially compatible with applicable standards regarding modular equipment. In...
US-9,437,466 Storage container, shutter opening/closing unit of storage container, and wafer stocker using storage container...
Provided is a wafer stocker that can prevent the inflow of an external atmosphere, maintain a wafer storage space at a desired atmosphere with a relatively...
US-9,437,465 Substrate processing apparatus and method of manufacturing semiconductor device
When a step is delayed, an operator can be rapidly informed of the delay. A substrate processing apparatus comprises a process system configured to process a...
US-9,437,464 Substrate treating method for treating substrates with treating liquids
A method for treating substrates with treating liquids, using a treating tank for storing the treating liquids, a holding mechanism for holding the substrates...
US-9,437,463 Heating device
A heating apparatus includes a susceptor having a heating face of heating a semiconductor and a supporting part joined with a back face of the susceptor. The...
US-9,437,462 Underfill material and method for manufacturing semiconductor device by using the same
A method for manufacturing a semiconductor device by using underfill material includes: a semiconductor chip mounting step configured to mount a semiconductor...
US-9,437,461 Semiconductor device and method for manufacturing the same
Aspects of the invention include a semiconductor device that enables both solder-outflow prevention and inhibition of seizures coming from laser processing...
US-9,437,460 Method for manufacturing semiconductor device
Entry of resin into a cylindrical electrode can be suppressed without excessively increasing the number of parts and without unnecessarily damaging members. For...
US-9,437,459 Aluminum clad copper structure of an electronic component package and a method of making an electronic...
An electronic component package that includes a package substrate having an aluminum bond pad formed from an aluminum clad copper structure. The aluminum clad...
US-9,437,458 Method of electrically isolating leads of a lead frame strip
A lead frame strip includes a plurality of connected unit lead frames, each unit lead frame having a die paddle and a plurality of leads connected to a...
US-9,437,457 Chip package having a patterned conducting plate and method for forming the same
According to an embodiment of the present invention, a chip package is provided. The chip package includes: a patterned conducting plate having a plurality of...
US-9,437,456 Heat treatment apparatus emitting flash of light
Flash lamps connected to short-pulse circuits and flash lamps connected to long-pulse circuits are alternately arranged in a line. The duration of light...
US-9,437,455 Manufacturing method for semiconductor device
A manufacturing method for a semiconductor device includes introducing an impurity into a SiC substrate, forming a mixed material layer, which is made from a...
US-9,437,454 Wiring board, semiconductor device, and manufacturing methods thereof
It is an object to reduce defective conduction in a wiring board or a semiconductor device whose integration degree is increased. It is another object to...
US-9,437,453 Control of wafer surface charge during CMP
CMP selectivity, removal rate, and uniformity are controlled both locally and globally by altering electric charge at the wafer surface. Surface charge...
US-9,437,452 Method of forming a fine pattern by using block copolymers
A method of forming a fine pattern includes forming a phase separation guide layer on a substrate, forming a neutral layer on the phase separation guide layer,...
US-9,437,451 Radical-component oxide etch
A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing...
US-9,437,450 Plasma etching method
In a plasma etching method, with respect to a substrate to be processed, which has a base layer, a silicon oxide film, and an etching mask formed in this order,...
US-9,437,449 Uniform, damage free nitride etch
An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be...
US-9,437,448 Substrate treatment method and substrate treating apparatus
A hydrofluoric acid is supplied to a surface of a substrate, and a native oxide film formed on the surface is corroded to be removed, exposing silicon in the...
US-9,437,447 Method for patterning a substrate for planarization
Techniques disclosed herein include increasing pattern density for creating high-resolution contact openings, slots, trenches, and other features. A conformal...
US-9,437,446 Slurry for chemical mechanical polishing and chemical mechanical polishing method
The present invention provides a slurry for chemical mechanical polishing, containing abrasive grain (a), compound (b) having an amino group having a pKa of...
US-9,437,445 Dual fin integration for electron and hole mobility enhancement
A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed...
US-9,437,444 Semiconductor device having hard mask structure and fine pattern and forming method thereof
A method for fabricating a semiconductor device includes forming a plurality of first hard mask patterns separated by a plurality of trenches on a target layer,...
US-9,437,443 Low-temperature sidewall image transfer process using ALD metals, metal oxides and metal nitrides
A SIT method includes the following steps. An SIT mandrel material is deposited onto a substrate and formed into a plurality of SIT mandrels. A spacer material...
US-9,437,442 Methods for polishing phase change materials
A slurry for polishing a phase change material, such as Ge--Sb--Te, or germanium-antimony-tellurium (GST), includes abrasive particles of sizes that minimize at...
US-9,437,441 Methods for etching substrate and semiconductor devices
A method of etching a substrate using a metal-assisted chemical etching process is provided. The method may include forming a metal catalytic layer to a...
US-9,437,440 Method for manufacturing a semiconductor device
A method for producing a semiconductor device is provided. The method includes: forming in a semiconductor substrate a plurality of semiconductor mesas...
US-9,437,439 Processing method for wafer having chamfered portion along the outer circumference thereof followed by thinning...
A wafer processing method for reducing the thickness of a wafer to a predetermined thickness, the wafer having a chamfered portion along the outer circumference...
US-9,437,438 Electroless plating process and tin-silver plating solution therein
An electroless plating process includes providing a semiconductor substrate which has a substrate and a copper pillar disposed on the substrate; providing a...
US-9,437,437 Method for producing semiconductor device by plating processing
According to one embodiment, a method for producing a semiconductor device includes forming a base film above a semiconductor substrate, forming a core above...
US-9,437,436 Replacement metal gate FinFET
A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a...
US-9,437,435 LTPS TFT having dual gate structure and method for forming LTPS TFT
The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature...
US-9,437,434 Semiconductor device and fabrication method thereof
A semiconductor device includes an inter-layer dielectric (ILD) layer over a substrate; and a first gate feature in the ILD layer, the first gate feature...
US-9,437,433 Method and apparatus for cooling wafer in ion implantation process
Embodiments of method for cooling a wafer in an ion implantation process are provided. A method for cooling the wafer in the ion implantation process includes...
US-9,437,432 Self-compensating oxide layer
A method of conformally doping a device on a semiconductor workpiece is disclosed. An oxide layer is applied to all surfaces of the device. Further, the...
US-9,437,431 Electronic device manufacture
New methods are provided for manufacturing a semiconductor device. Preferred methods of the invention include depositing a photoresist on a semiconductor...
US-9,437,430 Thick pseudomorphic nitride epitaxial layers
Semiconductor structures are fabricated to include strained epitaxial layers exceeding a predicted critical thickness thereof.
US-9,437,429 Polycrystalline silicon manufacturing apparatus and polycrystalline silicon manufacturing method
In order to obtain a polycrystalline silicon rod having an excellent shape, the placement relation between a source gas supplying nozzle 9 and metal electrodes...
US-9,437,428 Method of manufacturing a semiconductor device having an oxide semiconductor layer with increased hydrogen...
To provide a method for manufacturing a semiconductor device including an oxide semiconductor film having conductivity, or a method for manufacturing a...
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