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Patent # Description
US-9,437,325 TFT array substrate, display panel and display device
A TFT array substrate is disclosed. The TFT array substrate includes a plurality of gate lines, and a gate driving circuit connected to the gate lines. The gate...
US-9,437,324 Shift register unit, driving method thereof, shift register and display device
Embodiments of the present invention provides a shift register unit, driving method thereof, a shift register and a display device. A switch-off module is...
US-9,437,323 Shift register circuit for preventing malfunction due to clock skew and memory device including the same
A shift register circuit may include a first latch capable of latching an input signal in synchronization with a first clock, a first flip-flop capable of...
US-9,437,322 Circuit and method for reducing write disturb in a non-volatile memory device
An active precharge circuit for a non-volatile memory array which minimizes write disturb to non-selected memory cells during programming is disclosed. In a...
US-9,437,321 Error detection method
Methods for detecting and correcting defects in a memory array during a memory operation are described. The memory operation may comprise a programming...
US-9,437,320 Joint detecting and decoding system for nonvolatile semiconductor memory with reduced inter-cell interference
A system including a receiving module to receive data from cells of memory, each cell storing multiple bits, each bit corresponding to a different type of page...
US-9,437,319 Method for programming non-volatile memory with reduced bit line interference and associated device
Provided are methods, devices, and/or the like for reducing the bit line interference when programming non-volatile memory. One method comprises providing a...
US-9,437,318 Adaptive program pulse duration based on temperature
Techniques are provided for reducing program disturb in a memory device. The techniques include compensating for a temperature in the memory device to reduce...
US-9,437,317 Nonvolatile memory device, memory system having the same, external power controlling method thereof
An external power control method includes determining whether to apply a second external voltage to a first node according to a drop of a first external...
US-9,437,316 Continuous adjusting of sensing voltages
The present disclosure includes apparatuses and methods for continuous adjusting of sensing voltages. A number of embodiments include continuously monitoring an...
US-9,437,315 Data storing system and operating method thereof
A data storing system includes a semiconductor device suitable for repeatedly performing a read operation by changing a level of a read voltage according to...
US-9,437,314 Precharge control signal generator and semiconductor memory device therewith
A precharge control signal generator and a semiconductor memory device include a precharge control signal generating circuit which generates a precharge control...
US-9,437,313 Non-volatile memory device and related read method using adjustable bit line connection signal
A nonvolatile memory device comprises a memory cell array and a voltage generator. The memory cell array comprises a plurality of memory cells connected in...
US-9,437,312 Management of write-protected data in a semiconductor memory
Systems and methods of finalizing a semiconductor memory are disclosed. A method includes receiving an instruction to finalize data at a data storage device...
US-9,437,311 Flash memory apparatus and initialization method for programming operation thereof
A flash memory apparatus and an initialization method for programming operation thereof are provided. The initialization method includes: providing a plurality...
US-9,437,310 Method of operating a memory system having an erase control unit
A method of operating a memory system including a nonvolatile memory including a memory block, and a memory controller including an erase control unit, includes...
US-9,437,309 Operating method of NAND flash memory unit
A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer,...
US-9,437,308 Nonvolatile semiconductor memory device which performs improved erase operation
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a...
US-9,437,307 Nonvolatile semiconductor memory device
A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control...
US-9,437,306 NAND array architecture for multiple simutaneous program and read
This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal3 global bit lines (GBLs), divided metal2 Segment bit lines...
US-9,437,305 Programming memory with reduced short-term charge loss
Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in...
US-9,437,304 Memory devices and programming memory arrays thereof
An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first...
US-9,437,303 Programming method of memory array
A programming method of a memory array is provided and includes following steps, wherein the memory array includes a target memory cell and two periphery memory...
US-9,437,302 State-dependent lockout in non-volatile memory
A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier...
US-9,437,301 Non-volatile semiconductor memory device
According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality...
US-9,437,300 Semiconductor memory device
A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second...
US-9,437,299 Systems and methods for order scope transitions using cam
A data processing system includes a content addressable memory (CAM). Each entry of the CAM corresponds to a task and is configured to store a current scope of...
US-9,437,298 Self-storing and self-restoring non-volatile static random access memory
An apparatus is provided which comprises: a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated...
US-9,437,297 Write and erase scheme for resistive memory device
A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of...
US-9,437,296 Three-dimensional resistive memory device with adjustable voltage biasing
A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes: a plurality of...
US-9,437,295 Semiconductor system including semiconductor memory apparatus and temperature control method thereof
A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment...
US-9,437,294 Resistance variable memory sensing
The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell...
US-9,437,293 Integrated setback read with reduced snapback disturb
Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus...
US-9,437,292 Circuits and methods for limiting current in random access memory cells
Circuits and methods for limiting cell current or throttling write operation, or both, in resistive random access memory (RRAM or ReRAM) cells are provided. An...
US-9,437,291 Distributed cascode current source for RRAM set current limitation
In one example, a current limited device is coupled between a source line of a memory cell array and a supply voltage, and configured to operate in a constant...
US-9,437,290 Resistive memory device and operation
A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory...
US-9,437,289 Electronic device
Provided an electronic device including a semiconductor memory unit. The semiconductor memory unit includes: a plurality of storage cells each including a...
US-9,437,288 Dual mode clock and data scheme for memory programming
A Phase-Change Memory (PCM) includes a factory programming interface to receive data changing on both a positive transition and a negative transition of a dual...
US-9,437,287 Methods, devices and processes for multi-state phase change devices
Devices include multiple phase change materials connected in parallel between electrodes. Memory cells with multiple parallel phase change materials can be...
US-9,437,286 Memory system, method of programming the memory system, and method of testing the memory system
A method of programming a memory system includes repetitively performing N program loops for a selected memory cell (where N is a natural number equal to or...
US-9,437,285 Write address synchronization in 2 read/1write SRAM arrays
An aspect relates to a memory array that includes at least a first and a second six transistor static random access memory cell, and first and second address...
US-9,437,284 Memory devices and control methods thereof
A memory device is provided. The memory device includes a memory device, a plurality of word lines and bit lines, first and second decoders, and a control...
US-9,437,283 Semiconductor storage device
The disclosed invention provides a semiconductor storage device that creates no trouble, independently of power-on sequence. A semiconductor storage device...
US-9,437,282 High performance sense amplifier
A sense amplifier device for sensing a differential signal produced by a memory cell includes a first n-type metal-oxide-semiconductor field-effect transistor...
US-9,437,281 Negative bitline boost scheme for SRAM write-assist
A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the...
US-9,437,280 DRAM sense amplifier that supports low memory-cell capacitance
The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell...
US-9,437,279 Memory controller with clock-to-strobe skew compensation
A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at...
US-9,437,278 Low latency synchronization scheme for mesochronous DDR system
A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock...
US-9,437,277 Mechanism for data generation in data processing systems
An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value...
US-9,437,276 Maintenance operations in a DRAM
A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory...
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