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Patent # Description
US-9,443,972 Semiconductor device with field electrode
A method of producing a semiconductor device includes providing a semiconductor body having a first surface and a dielectric layer arranged on the first surface...
US-9,443,971 Semiconductor to metal transition
A semiconductor device includes a diffusion barrier layer, a first semiconductor region having first charge carriers of a first conductivity type and a second...
US-9,443,970 Semiconductor device with epitaxial structures and method for fabricating the same
A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a...
US-9,443,969 Transistor having metal diffusion barrier
A transistor includes a substrate, a channel layer over the substrate, an active layer over the channel layer, a metal diffusion barrier over the active layer,...
US-9,443,968 High electron mobility transistors including lightly doped drain regions and methods of manufacturing the same
High electron mobility transistors (HEMTs) including lightly doped drain (LDD) regions and methods of manufacturing the same. A HEMT includes a source, a drain,...
US-9,443,967 Semiconductor device having metal layer and method of fabricating same
A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate,...
US-9,443,966 High breakdown voltage semiconductor device
An n-type region encloses an n-type well region is disclosed in which is disposed a high-side drive circuit. A high resistance polysilicon thin film configuring...
US-9,443,965 Method for producing a thin film transistor
A method for producing a thin film transistor includes forming a transistor prototype on a substrate. The transistor prototype includes two transparent...
US-9,443,964 Fin structure of FinFet
A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the...
US-9,443,963 SiGe FinFET with improved junction doping control
A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a...
US-9,443,962 Recessing STI to increase fin height in fin-first process
A method includes forming a gate stack over top surfaces of a semiconductor strip and insulation regions on opposite sides of the semiconductor strip. The...
US-9,443,961 Semiconductor strips with undercuts and methods for forming the same
An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second...
US-9,443,960 Semiconductor device and fabrication method thereof
An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an...
US-9,443,959 Transistor structure with feed-through source-to-substrate contact
An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for...
US-9,443,958 High voltage metal-oxide-semiconductor transistor device and method of forming the same
A HVMOS transistor device is provided. The HVMOS has a substrate, a gate structure, a drain region and a source region, a base region and a gate dielectric...
US-9,443,957 Self-aligned source and drain regions for semiconductor devices
A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate...
US-9,443,956 Method for forming air gap structure using carbon-containing spacer
A method includes forming a line feature above a substrate. Carbon-containing spacers are formed on sidewalls of the line feature. A first dielectric layer is...
US-9,443,955 Semiconductor device and method for fabricating the same
Provided is a semiconductor device. Two stack layers are disposed on a substrate of a first conductivity type. Each of stack layers includes a dielectric layer...
US-9,443,954 Method for manufacturing semiconductor device having metal gate
The present invention provides a method for forming a semiconductor device having a metal gate. The method includes firstly, a substrate is provided, and a...
US-9,443,953 Sacrificial silicon germanium channel for inversion oxide thickness scaling with mitigated work function...
A technique relates to forming a transistor. A dummy gate is formed on a substrate with spacers on both sides. A source and a drain are formed in the substrate,...
US-9,443,952 Method of forming semiconductor device
A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap...
US-9,443,951 Embedded planar source/drain stressors for a finFET including a plurality of fins
Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed...
US-9,443,950 Semiconductor device
A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode...
US-9,443,949 Techniques for multiple gate workfunctions for a nanowire CMOS technology
In one aspect, a method of forming a CMOS device with multiple transistors having different Vt's is provided which includes: forming nanowires and pads on a...
US-9,443,948 Gate-all-around nanowire MOSFET and method of formation
A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a...
US-9,443,947 Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various...
A semiconductor chip includes a region that includes a first conductive structure (CS) that forms a gate electrode (GE) of a first transistor of a first...
US-9,443,946 Method of manufacturing an embedded split-gate flash memory device
A method of manufacturing an embedded split-gate flash memory device is provided. The method includes: performing shallow trench isolation and chemical...
US-9,443,945 Transistor including a gate electrode extending all around one or more channel regions
A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the...
US-9,443,944 Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and...
Devices and methods for forming semiconductor devices with middle of line capacitance reduction in self-aligned contact process flow and fabrication are...
US-9,443,943 Semiconductor device and fabrication method thereof
The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The...
US-9,443,942 Semiconductor device
A power diode is disclosed wherein it is possible to lower on-voltage by expanding a conducting region at an on time. By applying negative voltage to a plate...
US-9,443,941 Compound semiconductor transistor with self aligned gate
A transistor device includes a compound semiconductor body having a first surface and a two-dimensional charge carrier gas disposed below the first surface in...
US-9,443,940 Defect reduction with rotated double aspect ratio trapping
A structure and method for fabricating a heteroepitaxially grown lattice-mismatched semiconductor layer with a lower defect density is disclosed. A first...
US-9,443,939 Strain compensated REO buffer for III-N on silicon
A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide...
US-9,443,938 III-nitride transistor including a p-type depleting layer
A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further...
US-9,443,937 Semiconductor device
A semiconductor device according to an embodiment includes a SiC layer including a first region provided at a surface. The first region satisfies...
US-9,443,936 Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains
Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a...
US-9,443,935 Method of fabricating fin-field effect transistors (finFETs) having different fin widths
Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin...
US-9,443,934 Semiconductor device and manufacturing method thereof
To provide a transistor having high field effect mobility. To provide a transistor having stable electrical characteristics. To provide a transistor having low...
US-9,443,933 Matching of transistors
The present invention relates to a pair of transistors wherein each transistor of said transistor pair is made of several sub-transistors, and each...
US-9,443,932 Semiconductor device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a plurality of unit cells provided on a...
US-9,443,931 Fabricating stacked nanowire, field-effect transistors
Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate...
US-9,443,930 Semiconductor device and method of fabricating the same
A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to...
US-9,443,929 Shallow trench isolation structure having a nitride plug
A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically,...
US-9,443,928 Oxide terminated trench MOSFET with three or four masks
An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are...
US-9,443,927 Semiconductor device
A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed in the substrate at two respectively...
US-9,443,926 Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor
A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. The transistor comprises a terminal structure (200) and an...
US-9,443,925 Semiconductor structure with dielectric-sealed doped region
Leakage current can be substantially reduced by the formation of a seal dielectric in place of the conventional junction between source/drain region(s) and the...
US-9,443,924 Substrate with crystallized silicon film and manufacturing method thereof
The present invention relates to a substrate with a crystallized silicon film and manufacturing method thereof, wherein the substrate with the crystallized...
US-9,443,923 Substrate for molecular beam epitaxy (MBE) HgCdTe growth
A semiconductor structure having a first semiconductor body having an upper surface with a non <211> crystallographic orientation and a second...
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