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Patent # Description
US-9,443,872 Semiconductor device
Provided is a semiconductor device suitable for miniaturization and higher density. The semiconductor device includes a first transistor, a second transistor...
US-9,443,871 Cointegration of bulk and SOI semiconductor devices
A method of forming a semiconductor device structure includes providing a substrate with a semiconductor-on-insulator (SOI) configuration, the SOI substrate...
US-9,443,870 Semiconductor device and method of manufacturing the same
In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor...
US-9,443,869 Systems and methods for a semiconductor structure having multiple semiconductor-device layers
A multilayer semiconductor device structure comprising a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide is...
US-9,443,868 Semiconductor memory device and method of manufacturing the same
According to an embodiment, a semiconductor memory device comprises: a memory string comprising memory cells; and a contact electrically connected to one end of...
US-9,443,867 Method of making damascene select gate in memory device
A method of fabricating a memory device includes forming a mask over a top surface of a stack of alternating insulating material layers and control gate...
US-9,443,866 Mid-tunneling dielectric band gap modification for enhanced data retention in a three-dimensional semiconductor...
A tunneling dielectric layer for a vertical memory device is formed with a stack that provides a barrier height profile for high data retention tolerance....
US-9,443,865 Fabricating 3D NAND memory having monolithic crystalline silicon vertical NAND channel
Disclosed herein are techniques for fabricating 3D NAND memory devices having a mono-crystalline silicon semiconductor vertical NAND channel. Memory holes are...
US-9,443,864 Self-aligned floating gate in a vertical memory structure
A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body...
US-9,443,863 Semiconductor devices
Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on...
US-9,443,862 Select gates with select gate dielectric first
A NAND flash memory includes a select transistor having a first region formed of a stack of layers on the substrate surface, and a second region that includes...
US-9,443,861 Fluorine-blocking insulating spacer for backside contact structure of three-dimensional memory structures
Electrical shorts caused by diffusion of residual fluorine in metallic layers can be retarded or eliminated by forming fluorine-blocking structures. A stack of...
US-9,443,860 Semiconductor device having E-fuse and method for fabricating the same
An e-fuse including a substrate including a first active region and a second active region which are spaced from each other by an isolation region, a first...
US-9,443,858 Semiconductor device having buried bit lines and method for fabricating the same
A semiconductor device includes semiconductor bodies formed substantially perpendicular to a semiconductor substrate, buried bit lines formed in the...
US-9,443,857 Vertical fin eDRAM
Systems and methods of forming semiconductor devices. A trench capacitor comprising deep trenches is formed in an n+ type substrate. The deep trenches have a...
US-9,443,856 Semiconductor device and fabricating the same
The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having...
US-9,443,855 Spacer formation on semiconductor device
A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel...
US-9,443,854 FinFET with constrained source-drain epitaxial region
A method includes forming a plurality of fins on a substrate, conformally depositing a nitride liner above and in direct contact with the plurality of fins and...
US-9,443,853 Minimizing shorting between FinFET epitaxial regions
The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in...
US-9,443,852 Integrated circuit devices with source/drain regions including multiple segments
Integrated circuit devices with source/drain regions including multiple segments and methods of forming the same are provided. The integrated circuit devices...
US-9,443,851 Semiconductor devices including finFETs and local interconnect layers and methods of fabricating the same
Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a finFET, a metal routing layer, a first local...
US-9,443,850 Epitaxial growth between gates
An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between two gate...
US-9,443,849 Semiconductor electronic components with integrated current limiters
An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage...
US-9,443,848 Methods for contact formation for 10 nanometers and beyond with minimal mask counts
A method of making a semiconductor device includes depositing a hard mask on a dielectric layer on a substrate, the dielectric layer being disposed around...
US-9,443,847 Epitaxial formation of source and drain regions
An integrated circuit includes a gate structure disposed over a substrate. The integrated circuit further includes a silicon-containing material structure...
US-9,443,846 Dual trench rectifier and method for forming the same
A structure of dual trench rectifier comprises of the following elements. A plurality of trenches are formed parallel in an n- epitaxial layer on an n+...
US-9,443,845 Transistor body control circuit and an integrated circuit
An integrated circuit comprises a transistor body control circuit for controlling a body of a bidirectional power transistor. The transistor body control...
US-9,443,844 Gain cell semiconductor memory device and driving method thereof
A memory cell including two transistors and one capacitor, which is known as a gain cell, is improved. One electrode of the capacitor is connected to a bit...
US-9,443,843 Integrated circuit device
The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first...
US-9,443,842 Integrated circuit device
The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first...
US-9,443,841 Electrostatic discharge protection structure capable of preventing latch-up issue caused by unexpected noise
An electrostatic discharge protection structure comprises an isolation layer, a high voltage P-well, an N-well, a P-well, a first doped region of N-type...
US-9,443,840 Methods and apparatus for ESD structures
Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in...
US-9,443,839 Semiconductor device including gate drivers around a periphery thereof
A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal...
US-9,443,838 Method of fabricating integrated circuits, integrated circuit component mask layout set, and component...
A method of fabricating integrated circuits includes the steps of: a) with reference to a physical design of a hardware unit, preparing an integrated circuit...
US-9,443,837 Z-connection for a microelectronic package using electroless plating
An assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically...
US-9,443,836 Forming pixel units of image sensors through bonding two chips
A device includes a first chip including an image sensor therein, and a second chip bonded to the first chip. The second chip includes a logic device selected...
US-9,443,835 Methods for performing embedded wafer-level packaging (eWLP) and eWLP devices, packages and assemblies made by...
Embedded Wafer-Level Packaging (eWLP) methods and optoelectronic devices, packages and assemblies made by the eWLP methods are described. The eWLP methods allow...
US-9,443,834 Back-to-back solid state lighting devices and associated methods
Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can...
US-9,443,833 Transparent overlapping LED die layers
A first layer of inorganic first vertical LED dies (VLEDs) of a first color is printed on a conductor surface. A first transparent conductor layer is deposited...
US-9,443,832 Light emitting device, light source for illumination, and illumination apparatus
A light emitting device includes: a substrate; a first light emitting element and a second light emitting element that are mounted above the substrate; and a...
US-9,443,831 Substrate for mounting LED element, LED light source and LED display
Provided is a substrate for mounting an LED element in which a stable light-emitting surface is obtained, as well as a light source and an LED display using...
US-9,443,830 Printed circuits with embedded semiconductor dies
Electrical components such as semiconductor die may be mounted in semiconductor packages and embedded within printed circuits. A printed circuit may have a...
US-9,443,829 Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structure
A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of...
US-9,443,828 Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat...
A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is...
US-9,443,827 Semiconductor device sealed in a resin section and method for manufacturing the same
A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first...
US-9,443,826 Stack package and reduction of standby current
The stack package includes: a plurality of chips each stacked with a plurality of layers; and a plurality of pads respectively formed on the plurality of chips....
US-9,443,825 Multi-function miniaturized surface-mount device and process for producing the same
A surface-mount device (SMD) uses no conventional lead frame and contains a multi-function die module formed from either a single die or two or more dies...
US-9,443,824 Cavity bridge connection for die split architecture
An integrated circuit (IC) package structure may include a substrate. The substrate may include a semiconductor bridge having a first surface directly on a...
US-9,443,823 Semiconductor device including filling material provided in space defined by three semiconductor chips
A semiconductor device comprises a wiring substrate, first and second semiconductor chips mounted on the wiring substrate so as to be spaced apart from each...
US-9,443,822 Flip chip assembly and process with sintering material on metal bumps
A method is disclosed of fabricating a microelectronic package comprising a substrate overlying the front face of a microelectronic element. A plurality of...
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