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Patent # Description
US-9,443,771 Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology
A method of removing RMG sidewall layers, and the resulting device are provided. Embodiments include forming a TiN layer in nFET and pFET RMG trenches; forming...
US-9,443,770 Patterning process for fin implantation
After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is...
US-9,443,769 Wrap-around contact
Fin structures are formed on a substrate. An isolation region is between the fin structures. The fin structures comprise epitaxial regions extending above the...
US-9,443,768 Method of making a FinFET device
A method of fabricating a fin-like field-effect transistor (FinFET) device includes providing a substrate having a first region and a second region, and forming...
US-9,443,767 Structure for metal oxide semiconductor capacitor
A design structure for a semiconductor structure is disclosed. The semiconductor structure can include a substrate, a set of semiconductor fins positioned on...
US-9,443,766 Method for manufacturing diode
A diode manufacturing method provided herein includes first-third implantations and a heating. The first implantation implants n-type impurities into a first...
US-9,443,765 Water soluble mask formation by dry film vacuum lamination for laser and plasma dicing
Methods and systems for dicing a semiconductor wafer including a plurality of integrated circuits (ICs) are described. In one embodiment, a method involves...
US-9,443,764 Method of eliminating poor reveal of through silicon vias
A method and structure for eliminating through silicon via poor reveal is disclosed. In one embodiment, the method includes obtaining a wafer having a front...
US-9,443,763 Methods for forming interconnections between top electrodes in memory cells by a two-step chemical-mechanical...
Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a...
US-9,443,762 Semiconductor device and method of forming a thin wafer without a carrier
A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate....
US-9,443,761 Methods for fabricating integrated circuits having device contacts
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes providing a semiconductor...
US-9,443,760 Multichip power semiconductor device
An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted...
US-9,443,759 Method for producing a semiconductor device comprising a conductor layer in the semiconductor body and...
A cutout (11), which penetrates the semiconductor body, is present in the semiconductor body (1). A conductor layer (6), which is electrically conductively...
US-9,443,758 Connecting techniques for stacked CMOS devices
A stacked integrated circuit includes multiple tiers vertically connecting together. A multi-layer horizontal connecting structure is fabricated inside a...
US-9,443,757 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon;...
US-9,443,756 Methods of forming a substrate opening
A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side...
US-9,443,755 Method of fabricating miniaturized semiconductor or other device
A method of fabricating a miniaturized semiconductor or other such device takes advantage of a self-reorganization characteristic of an in-situ dissociable...
US-9,443,754 Semiconductor device including high-voltage diode
A semiconductor device includes a substrate, a high-voltage N-well (HVNW) disposed in the substrate, a bulk P-well disposed in the substrate and adjacent to an...
US-9,443,753 Apparatus for controlling the flow of a gas in a process chamber
Apparatus for controlling the flow of a gas in a process chamber is provided herein. In some embodiments, an apparatus for controlling the flow of a gas in a...
US-9,443,752 High temperature anti-droop end effector for substrate transfer
Embodiments of the present invention relates to high temperature anti-droop end effectors for transferring semiconductor substrates. One embodiment of the...
US-9,443,751 Back grinding sheet
The present invention relates to a back grinding sheet (BG sheet) (1a, 1b, 1c) having an unevenness-absorbing layer (12) on a substrate (11), in which the...
US-9,443,750 Dicing sheet with protective film-forming layer, and method for producing chip
A dicing sheet with a protective film-forming layer includes a protective film-forming layer on an adhesive layer of an adhesive sheet with a peel strength...
US-9,443,749 Vacuum processing apparatus
In this vacuum processing apparatus, four process modules and four load-rock modules are arranged in clusters around a two-stage conveyance vacuum chamber. In...
US-9,443,748 Substrate processing apparatus, program for controlling the same, and method for fabricating semiconductor device
A substrate processing apparatus includes a mounting stand, a cover opening and closing unit, a substrate checking unit, a substrate transfer mechanism, a...
US-9,443,747 Apparatus for transferring and manipulating semiconductor components
An apparatus for picking and placing or for picking and transferring or for picking, placing and pressing semiconductor components (10) is disclosed. The...
US-9,443,746 Floating mold tool for semicondcutor packaging
Tooling for molding a packaged semiconductor device includes a clamping plate, a cavity bar, and an attachment mechanism. The cavity bar has a mold half that...
US-9,443,745 Method for setting coating module quantity and robot speed
The present invention relates to developing and design a coater & developer with high throughput that in-line with lithograph equipment during integrated...
US-9,443,744 Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods
A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a...
US-9,443,743 Method for directly attaching dielectric to circuit board with embedded electronic devices
A method for directly attaching dielectric to a circuit board with embedded electronic devices is provided. That is, a plurality of through holes are produced...
US-9,443,742 Patterned feature and multiple patterning method thereof
A multiple patterning method is provided. The multiple patterning method includes providing a substrate; and forming a sacrificial film on the substrate. The...
US-9,443,741 Etching method for reducing microloading effect
An etching method includes forming a high density structure and a low density structure on a substrate. A first material layer is formed to cover both...
US-9,443,740 Process for forming gate of thin film transistor devices
A process for forming a T-gate with enhanced mechanical strength and a reduced gate length for high electron mobility transistors is provided. The process...
US-9,443,739 Process for the manufacture of semiconductor devices comprising the chemical mechanical polishing of elemental...
A process for the manufacture of semiconductor devices comprising the chemical mechanical polishing of elemental germanium and/or Si.sub.1-xGe.sub.x material...
US-9,443,738 Integrated circuits with middle of line capacitance reduction in self-aligned contact process flow and...
Semiconductor devices and methods for forming the devices with middle of line capacitance reduction in self-aligned contact process flow are provided. One...
US-9,443,737 Method of forming metal contacts in the barrier layer of a group III-N HEMT
Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second...
US-9,443,736 Silylene compositions and methods of use thereof
A silicon precursor composition is described, including a silylene compound selected from among: silylene compounds of the formula: wherein each of R and...
US-9,443,735 Method of manufacturing semiconductor device
There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric...
US-9,443,734 Semiconductor memory devices and manufacturing methods thereof
A semiconductor memory device and a manufacturing method of the semiconductor memory device are provided. The semiconductor memory device can include a...
US-9,443,733 Method and apparatus for authenticating a semiconductor die
The present disclosure describes apparatuses and techniques for device-based die authentication. In some aspects, an intensity of a particle beam is varied...
US-9,443,732 Method of fabricating semiconductor device
The method may include forming a plurality of fins on a substrate with first and second regions, forming a photoresist pattern to expose the fins of the first...
US-9,443,731 Material processing to achieve sub-10nm patterning
Provided is a method for increasing pattern density on a substrate comprising a structure with a patterned layer with a first composition and a sidewall and a...
US-9,443,730 Process for forming silicon-filled openings with a reduced occurrence of voids
In some embodiments, silicon-filled openings are formed having no or a low occurrence of voids in the silicon fill, while maintaining a smooth exposed silicon...
US-9,443,729 Method for forming FinFET devices
A method comprises providing a substrate formed of a first semiconductor material, wherein the substrate comprises a plurality of isolation regions, etching...
US-9,443,728 Accelerated relaxation of strain-relaxed epitaxial buffers by use of integrated or stand-alone thermal processing
Implementations of the present disclosure generally relate to methods and apparatus for forming a film on a substrate. More particularly, implementations of the...
US-9,443,727 Semi-polar III-nitride films and materials and method for making the same
A method has been developed to overcome deficiencies in the prior art in the properties and fabrication of semi-polar group III-nitride templates, films, and...
US-9,443,726 Semiconductor process
A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a...
US-9,443,725 Multi-step system and method for curing a dielectric film
A multi-step system and method for curing a dielectric film in which the system includes a drying system configured to reduce the amount of contaminants, such...
US-9,443,724 Modification processing method and method of manufacturing semiconductor device
A modification processing method includes preparing a substrate having a silicon layer on which a damage layer is formed through plasma processing. The method...
US-9,443,723 Integrated circuits with an insultating layer and methods for producing such integrated circuits
Integrated circuits and methods for producing the same are provided. A method of producing the integrated circuits includes forming an insulating layer...
US-9,443,722 Cyclical, non-isobaric, pore sealing method to prevent precursor penetration into the substrate
A method for processing a substrate using a plasma chamber. The method includes providing the substrate on a pedestal of the plasma chamber, the substrate...
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