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Patent # Description
US-9,443,619 Strip for a nuclear fuel assembly spacer grid
The strip is of the type comprising a wall portion for delimiting a cell for receiving a fuel rod and allowing flow of a coolant upwardly through the spacer...
US-9,443,618 Semiconductor memory device mapping external address as internal address wherein internal addresses of spare...
Provided is a semiconductor memory device that may efficiently map an internal address used inside the semiconductor memory device in response to an external...
US-9,443,617 Memory system and method of controlling memory system
According to one embodiment, a controller includes a quality measuring unit, a block classifying unit, and a multi-plane setting unit. The quality measuring...
US-9,443,616 Bad memory unit detection in a solid state drive
An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of...
US-9,443,615 Methods and apparatuses for memory testing with data compression
Apparatuses and methods for memory testing with data compression is described. An example apparatus includes a plurality of latch test circuits, wherein each of...
US-9,443,614 Data pattern generation for I/O testing
One feature pertains to a single data pattern being read from a pattern register located within a memory circuit or device. At least one of the plurality of...
US-9,443,613 Advanced memory test diagnostics
For performing advanced memory test diagnostics, an apparatus, method, and computer program product are disclosed. The apparatus may include a processor, a...
US-9,443,612 Determination of bit line to low voltage signal shorts
A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of...
US-9,443,611 Semiconductor integrated circuit with bist circuit
According to an embodiment, a semiconductor integrated circuit includes a memory, a bypass circuit, a first selection unit, a compression unit, and a comparison...
US-9,443,610 Leakage current detection
A system includes a first switch, an amplifier, a second switch, and a capacitor. The first switch is electrically coupled between a first reference voltage and...
US-9,443,609 Voltage monitoring test circuit and voltage monitoring method using the same
A voltage monitoring test circuit includes a switching control signal generation unit configured to receive first and second switching signals, control the...
US-9,443,608 Shift register having multiple output units connected in cascade as display device scan line driving circuit
A shift register includes unit circuits connected in a cascade, and each of the unit circuits includes a logic circuit, a first output unit, and a second output...
US-9,443,607 Latch circuit and semiconductor device including the same
A latch circuit includes a write driving unit configured to output fuse data as boot-up data according to a fuse set select signal in a boot-up operation; and a...
US-9,443,606 Word line dependent two strobe sensing mode for nonvolatile storage elements
A non-volatile storage system includes a plurality of non-volatile storage elements, a plurality of bit lines connected to the non-volatile storage elements, a...
US-9,443,605 Temperature dependent voltage to unselected drain side select transistor during program of 3D NAND
Techniques are provided for reducing program disturb in a 3D memory device. The techniques include compensating for a temperature dependence of program disturb....
US-9,443,604 Electronic device and data-management method thereof
An exemplary embodiment provides an electronic device including a controller, a first flash memory and a second flash memory. The first flash memory stores a...
US-9,443,603 Storage device and related methods using timer setting
A storage device comprises at least one nonvolatile memory device and a memory controller configured to control the at least one nonvolatile memory device. The...
US-9,443,602 Storage device and data latch timing adjustment method
According to one embodiment, a storage device includes a storage medium, a DLL circuit, a latch circuit, and a delay amount adjustment circuit. The DLL circuit...
US-9,443,601 Holdup capacitor energy harvesting
The various embodiments described herein include circuits, methods and/or devices used to protect data in a storage device. In one aspect, a method includes...
US-9,443,600 Auto-suspend and auto-resume operations for a multi-die NAND memory device to reduce peak power consumption
A method and apparatus that controls a peak-current condition in a multi-die memory, such as a solid-state drive, by determining by at least one die of the...
US-9,443,599 Method of controlling erase operation of a memory and memory system implementing the same
A non-volatile memory and a method of controlling an erase operation of the non-volatile memory using a controller are provided. The method of controlling the...
US-9,443,598 Method for programming a non-volatile memory cell comprising a shared select transistor gate
The present disclosure relates to a method for controlling two twin memory cells each comprising a floating-gate transistor comprising a state control gate, in...
US-9,443,597 Controlling dummy word line bias during erase in non-volatile memory
A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data...
US-9,443,596 Non-volatile memory device and method of programming the same
A non-volatile memory device includes a memory cell array and a voltage generator. The memory cell array has a plurality of cell strings in which a plurality of...
US-9,443,595 Memory system and assembling method of memory system
According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit...
US-9,443,594 Logic embedded nonvolatile memory device
A logic embedded nonvolatile memory device is provided which includes a first erase gate line for erasing a plurality of first memory cells; a second erase gate...
US-9,443,593 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second...
US-9,443,592 Semiconductor device and method for manufacturing semiconductor device
A manufacturing method of a semiconductor device in which the threshold is corrected is provided. In a semiconductor device including a plurality of transistors...
US-9,443,591 Storage device out-of-space handling
Described embodiments detect an impending out-of-space (OOS) condition of a media. On startup, a media controller determines whether an impending OOS indicator...
US-9,443,590 Content addressable memory cells, memory arrays and methods of forming the same
A content addressable memory cell is provided that includes plurality of transistors having a minimum feature size F, and a plurality of memory elements coupled...
US-9,443,589 Method for capacitively reading resistive memory elements and nonvolatile, capacitively readable memory...
A method for reading out a non-volatile memory element having at least two stable states 0 and 1. This memory element comprises at least one resistive memory...
US-9,443,588 Resistive memory system, driver circuit thereof and method for setting resistance thereof
A resistive memory system, a driver circuit thereof and a method for setting resistances thereof are provided. The resistive memory system includes a memory...
US-9,443,587 Resistive memory apparatus and writing method thereof
A resistive memory apparatus and a writing method thereof are provided. In the method, logic data is received, and a corresponding resistive memory cell is...
US-9,443,586 Nonvolatile memory device, memory system including the same and method for driving nonvolatile memory device
A nonvolatile memory device can improve a read retry operation speed while minimizing a reduction in the capability of a memory read operation by performing a...
US-9,443,585 Resistance change memory
According to one embodiment, a resistance change memory includes a first memory cell, a word line, a first bit line, first and second inverters, first to sixth...
US-9,443,584 Network interface with logging
Structures and methods for improving logging in network structures are disclosed herein. In one embodiment, an apparatus can include: (i) a network interface...
US-9,443,583 Resistive memory and method
A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.
US-9,443,582 Nonvolatile memory device and method for testing nonvolatile memory device using variable resistance material
A method for testing a nonvolatile memory device includes: monitoring a first resistance dispersion and a second resistance dispersion of a nonvolatile memory...
US-9,443,581 Electronic device and method for fabricating the same
An electronic device includes a semiconductor memory, the semiconductor memory including: a substrate configured to comprise a plurality of line patterns which...
US-9,443,580 Multi-level cell memory
A multi-level cell memory includes a memory cell that stores two or more bits of information; a sensing circuit coupled to the memory cell; and a row buffer...
US-9,443,579 VSL-based VT-compensation and analog program scheme for NAND array without CSL
A YUKAI NAND array comprising multiple strings of all TLC and mixed TLC+SLC memory cells associated with hierarchical global/local bit lines (GBL/LBL) and each...
US-9,443,578 NAND array architecture for multiple simultaneous program and read
This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal3 global bit lines (GBLs), divided metal2 Segment bit lines...
US-9,443,577 Voltage-switched magnetic random access memory (MRAM) and method for using the same
The present invention is directed to a magnetic random access memory comprising a first magnetic tunnel junction (MTJ) including a first magnetic reference...
US-9,443,576 Josephson magnetic random access memory with an inductive-shunt
A memory system includes a word-line coupled to memory cells in a row, and a bit-line coupled to memory cells in a column. Each of the memory cells includes a...
US-9,443,575 Semiconductor memory
The disclosed invention provides an SRAM capable of stably generating a PUF-ID without having to be powered on/off under control. The SRAM including a plurality...
US-9,443,574 Memory architecture
A first current value flowing through a transistor coupled with a storage node of a memory cell is determined when the transistor is off. A second current value...
US-9,443,573 Semiconductor device including main amplifers between memory cell arrays
A semiconductor device includes a plurality of main amplifiers provided between memory cell arrays. One of the main amplifiers is disposed closer to one of the...
US-9,443,572 Programmable power for a memory interface
Systems and methods for delay control are described herein. In one embodiment, a delay system comprises a first delay circuit configured to provide a voltage...
US-9,443,571 Semiconductor memory, memory system and method of controlling semiconductor memory
According to one embodiment, a semiconductor memory includes a memory area; an error detection circuit which detect an error of first data output from the...
US-9,443,570 Memory apparatus with training function and memory system using the same
A memory apparatus includes a data receiver, a data delay unit, a strobe output unit, and a data latch unit. The data receiver may receive a plurality of...
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