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Patent # Description
US-9,442,866 Self-adaptive solid state drive controller
A memory device may comprise circuitry to determine a number of channels through which to transfer information to adjust between latency and throughput in...
US-9,442,865 Processor extensions for execution of secure embedded containers
Methods and apparatus relating to processor extensions for execution of secure embedded containers are described. In an embodiment, a scalable solution for...
US-9,442,864 Bridging circuitry between a memory controller and request agents in a system having multiple system memory...
A processor is described that includes one or more processing cores. The processor includes a memory controller to interface with a system memory having a...
US-9,442,863 Cache entry management using read direction detection
This document describes techniques for cache entry management using read direction detection. In one set of embodiment, the caching system segregates cache...
US-9,442,862 Polymorph table with shared columns
For managing a database in a data-processing system, a polymorph table and a mapping structure are provided. The polymorph table includes a discrimination...
US-9,442,861 System and method for out-of-order prefetch instructions in an in-order pipeline
Apparatuses, systems, and a method for providing a processor architecture with data prefetching are described. In one embodiment, a system includes one or more...
US-9,442,860 Providing record level sharing (RLS) to individual catalogs
In one embodiment, a data storage system includes a server system that includes a processor and a local buffer pool configured to store instances for use in...
US-9,442,859 Method for asynchronous population of data caches used with mass storage devices
A method and system for transferring data from mass storage devices to the high speed data cache in a manner that imposes minimal overhead to the normal...
US-9,442,858 Solid state drives as a persistent cache for database systems
Disclosed herein are systems, methods, and computer readable storage media for a database system using solid state drives as a second level cache. A database...
US-9,442,857 Dynamic memory estimations for memory bounded applications
Techniques are disclosed for improving application responsiveness, and particularly applications used to present rich media content, by precaching nearby but...
US-9,442,856 Data processing apparatus and method for handling performance of a cache maintenance operation
A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at...
US-9,442,855 Transaction layer packet formatting
A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is...
US-9,442,854 Memory circuitry including computational circuitry for performing supplemental functions
A computer system includes but is not limited to a primary processing circuitry, a bus coupled to the primary processing circuitry, and memory circuitry coupled...
US-9,442,853 Salvaging lock elision transactions with instructions to change execution type
A transactional memory system salvages a hardware lock elision (HLE) transaction. A processor of the transactional memory system executes a lock-acquire...
US-9,442,852 Programmable coherent proxy for attached processor
A coherent attached processor proxy (CAPP) within a primary coherent system participates in an operation on a system fabric of the primary coherent system on...
US-9,442,851 Multi-core processor system, control program, and control method
A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores...
US-9,442,850 Efficient directory refresh operations in wide area file systems
Methods, apparatuses, and systems directed to reducing network traffic and processing overhead associated with directory refresh operations in wide area network...
US-9,442,849 Apparatus and method for reduced core entry into a power state having a powered down core cache
A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the...
US-9,442,848 Increased destaging efficiency by smoothing destaging between current and desired number of destage tasks
Techniques for increased destaging efficiency by smoothing destaging tasks to reduce long input/output (I/O) read operations are described. A method may...
US-9,442,847 Increased destaging efficiency by smoothing destaging between current and desired number of destage tasks
Techniques for increased destaging efficiency by smoothing destaging tasks to reduce long input/output (I/O) read operations are described. A system may...
US-9,442,846 High speed memory systems and methods for designing hierarchical memory systems
A system and method for designing and constructing hierarchical memory systems is disclosed. A plurality of different algorithmic memory blocks are disclosed....
US-9,442,845 Encoding a data address using XOR operation wherein address bits are transformed by multiple preset polynomials
The present invention relates to the field of communication technologies and discloses a method and an apparatus for encoding a data address, so that attacks...
US-9,442,844 Apparatus, system, and method for a storage layer
A storage layer for a non-volatile storage device presents a large, logical address space having a logical capacity that may exceed the storage capacity of the...
US-9,442,843 Information processing apparatus, method of controlling the same, and storage medium
An information processing apparatus capable of reading/writing a storage device capable of performing dynamic wear leveling, a method of controlling the...
US-9,442,842 Memory system performance configuration
A nonvolatile memory die is tested to determine certain parameters such as read time, which are then recorded in the nonvolatile memory die. After the die is...
US-9,442,841 Semiconductor memory device and method for logging monitored events into a buffer
A semiconductor memory device includes a nonvolatile semiconductor memory in which writing is carried out at a page unit and erasing is carried out at a block...
US-9,442,840 Virtual boundary codes in a data image of a read-write memory device
Methods, systems and devices are provided for configuring a read-write memory device with a data image. The method includes determining a data image...
US-9,442,839 Nonvolatile storage with automated response to program faults
A non-volatile storage system comprises a controller and one or more memory die in communication with the controller. The controller sends data and an initial...
US-9,442,838 Remapping memory cells based on future endurance measurements
A method of operating a memory device that includes groups of memory cells is presented. The groups include a first group of memory cells. Each one of the...
US-9,442,837 Accelerating multiversion concurrency control using hardware transactional memory
Atomically updating shared data in a transactional memory system comprising transactional memory storage and a transactional memory enabled processor. The...
US-9,442,836 Arithmetic processing device, information processing device, control method for information processing device,...
An arithmetic processing device having an allocation unit configured to reserve a memory allocation area in a memory and register address range information...
US-9,442,835 Dynamic memory allocation using suballocation of cell blocks
A computer-implemented method is disclosed in which a memory suballocation application obtains, from an underlying memory allocation system (UMAS), allocation...
US-9,442,834 Data management method, memory controller and memory storage device
A data management method for a rewritable non-volatile memory module including a first memory unit and a second memory unit is provided. The method includes:...
US-9,442,833 Managing device identity
Enrolling a device identity is disclosed. A determination is made as to whether one or more areas of a storage device has a sufficient number of faults. If an...
US-9,442,832 User workflow replication for execution error analysis
Examples of workflow replication and execution error analysis are provided herein. Data describing how a user interacts with a software application and...
US-9,442,831 Automated testing of program code for processing a simple boot flag data structure
A computer is configured with a simple boot flag testing module. The simple boot flag testing module sets a simple boot flag data structure to a first value....
US-9,442,830 Automated test coverage analysis, execution and reporting
Described are techniques for testing software. The techniques may include identifying, at a first point in time, first code that has been modified, identifying,...
US-9,442,829 Detecting error states when interacting with web applications
Detecting error states when interacting with web applications is performed by accessing a first web page of a web application, determining that the first web...
US-9,442,828 Generating test scripts through application integration
This claimed subject matter relates to techniques for generating a test script from a pre-existing script for testing a graphical user interlace (GUI)...
US-9,442,827 Simulation environment for distributed programs
A dataflow of a distributed application is visualized in a locally simulated execution environment. A scheduler receives a job graph which includes a graph of...
US-9,442,826 Kernel functionality checker
A debugging system and method, referred to as a kernel functionality checker, is described for enabling debugging of software written for device-specific APIs...
US-9,442,825 Method and device for signing program crash
A method and a device for signing a program crash are disclosed, which are applied to the filed of communication technology. The device for signing the program...
US-9,442,824 Transformation of a program-event-recording event into a run-time instrumentation event
Embodiments of the invention relate to transforming a program-event-recording event into a run-time instrumentation event. An aspect of the invention includes...
US-9,442,823 Memory error tracking in a multiple-user development environment
A method for identifying code segments and associated software developers in a software development environment is disclosed. A software development tool...
US-9,442,822 Providing a visual representation of a sub-set of a visual program
To provide a visual representation of a sub-set of a visual program generated using a visual programming tool, wherein a trace operation is executed against the...
US-9,442,821 System and method to classify automated code inspection services defect output for defect analysis
A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming...
US-9,442,820 Computer-implemented methods and systems for testing online systems and content
Computer-implemented methods and systems are provided for scanning web sites and/or parsing web content, including for testing online opt-out systems and/or...
US-9,442,819 Method and apparatus for storing trace data
A method and apparatus for storing trace data within a processing system. The method includes configuring at least one Error Correction Code, ECC, component...
US-9,442,818 System and method for dynamic data collection
In one embodiment, a method is performed on a computer system comprising computer hardware. The method includes inserting, at an instrumentation point of a...
US-9,442,817 Diagnosis of application server performance problems via thread level pattern analysis
Performance of server that is managing a group of servers, such as in a cloud, is analyzed by identifying patterns of threads executed in the server. A command...
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