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Patent # Description
US-9,450,626 Sawless architecture for receivers
An apparatus including: at least one differential amplifier configured to amplify a radio frequency signal; a mixer configured to mix the radio frequency signal...
US-9,450,625 Methods, systems, and non-transitory computer readable media for wideband frequency and bandwidth tunable filtering
Methods, systems, and computer readable media for wideband frequency and bandwidth tunable filtering are disclosed. According to one aspect, the subject matter...
US-9,450,624 Interference cancellation and improved signal-to-noise ratio circuits, systems, and methods
Interference cancellation for wideband and narrowband communications systems is provided without apriori knowledge of statistical information about an...
US-9,450,623 Noise canceler for use in a transceiver
A noise canceler for use in a transceiver is disclosed. In an exemplary embodiment, an apparatus includes a split amplifier to output an amplified transmit...
US-9,450,622 Circuit and method for providing a radio frequency signal
A circuit for generating a radio frequency signal includes an amplifier configured to provide a radio frequency signal, the radio frequency signal being based...
US-9,450,621 Digital predistortion processing method and system
A digital predistortion processing method and system comprises extracting from a predistortion coefficient parameter table a predistortion parameter...
US-9,450,620 Fast indirect antenna control
A digital interface and control module and a multi-function digital bus for use in a wireless radio frequency receiver, transmitter, or transceiver that...
US-9,450,619 Dynamic log likelihood ratio quantization for solid state drive controllers
A method for system for dynamic channel Log Likelihood Ratio (LLR) quantization for a Solid State Drive (SSD) controller is a targeted approach to scaling which...
US-9,450,618 Max-Log-MAP equivalence log likelihood ratio generation soft Viterbi architecture system and method
A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for...
US-9,450,617 Distribution and replication of erasure codes
Example apparatus and methods selectively replicate some erasure codes associated with a message and selectively distribute, without replicating, other erasure...
US-9,450,616 Adaptive coded-modulation for intelligent optical transport networks
A computer implemented method for dynamic data rate adjustment within a cascaded forward error correction FEC for optical communications includes subjecting...
US-9,450,615 Multi-bit error correction method and apparatus based on a BCH code and memory system
Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly...
US-9,450,614 Memory module with integrated error correction
A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some...
US-9,450,613 Apparatus and method for error correction and error detection
A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits...
US-9,450,612 Encoding method and system for quasi-cyclic low-density parity-check code
A method and system are provided. The method includes applying a quasi-cyclic matrix M to an input vector X.sup.- of encoded data to generate a vector Y. The...
US-9,450,611 Low density parity check encoder having length of 64800 and code rate of 7/15, and low density parity check...
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory,...
US-9,450,610 High quality log likelihood ratios determined using two-index look-up table
A nonvolatile memory controller includes memory storage configured to store a two-index look-up table that includes a Log-Likelihood Ratio (LLR),...
US-9,450,609 Methods and apparatus for embedding an error correction code in memory cells
A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without...
US-9,450,608 Method and arrangement for coding transform coefficients in picture and/or video coders and decoders and a...
The present invention describes a method and an arrangement for coding transform coefficients in picture and/or video coders and decoders and a corresponding...
US-9,450,607 Encoding or decoding characters as word in corpus
Data may be decompressed by receiving a compressed sequence of characters, the compressed sequence of characters being represented by at least a first received...
US-9,450,606 Data matching for hardware data compression
Methods and apparatuses for generating match data for a symbol in a symbol history for use in a hardware-based data compressor. An apparatus for performing...
US-9,450,605 Block compression of tables with repeated values
Methods and apparatus, including computer program products, for block compression of tables with repeated values. In general, value identifiers representing a...
US-9,450,604 Elastic data packer
This disclosure relates to compressing and/or decompressing a group of similar data units, such as a table or queue of data units processed by a networking...
US-9,450,603 Compression of integer data using a common divisor
According to one embodiment of the present invention, a system for compressing data determines a common divisor for a set of values comprising integers. The...
US-9,450,602 Efficiently query compressed time-series data in a database
A query of time series data stored in a database is received that specifies at least one value. The database includes (i) an index table specifying groups of...
US-9,450,601 Continuous rounding of differing bit lengths
A system and method are disclosed for encoding numbers in a way that improves the accuracy and efficiency of one or more computing devices working with the...
US-9,450,600 Digital-analog converter and digital-analog conversion device executing digital-analog conversion after delta sigma
The DA converter according to the present invention includes: first and second analog segment units a plurality of capacitors of sampling capacitor groups...
US-9,450,599 Current digital-to-analog converter reducing flicker noise
A current DAC circuit includes a reference current source, a current mirror, a decoder, and one or more current DAC units. The reference current source provides...
US-9,450,598 Two-stage digital down-conversion of RF pulses
A two-stage digital down-conversion device for optimal detection of varying RF pulses incorporates a front end analog to digital converter (ADC), which samples...
US-9,450,597 Hardware based compressive sampling ADC architecture for non-uniform sampled signal recovery
A back end-circuit for randomized non uniform and alias-free subsampling, comprising: an analog-to-digital converter (ADC) configured for sampling an input...
US-9,450,596 Ramp and successive approximation register analog to digital conversion methods, systems and apparatus
Successive approximation register (SAR) and ramp analog to digital conversion (ADC) methods, systems, and apparatus are disclosed. An analog voltage signal may...
US-9,450,595 N-path cascode transistor output switch for a digital to analog converter
Techniques are provided for a switched output digital to analog converter employing an N-path cascode output switch. An example system may include a plurality...
US-9,450,594 Time difference adders, time difference accumulators, sigma-delta time-to-digital converters, digital phase...
A time difference adder included in a system-on-chip (SOC) includes a first register unit and a second register unit. The first register unit is configured to...
US-9,450,593 Dither-less error feedback fractional-n frequency synthesizer systems and methods
A fractional-N divider of a frequency synthesizer is driven by a dither-less error feedback modulator to alleviate fractional spurious tones introduced by the...
US-9,450,592 Frequency control system with dual-input bias generator to separately receive management and operational controls
Methods and systems to control an output frequency relative to a reference frequency. A frequency control system includes a dual-input bias generator to...
US-9,450,591 Adjusting voltage controlled oscillator gain
Apparatus and methods for adjusting a gain of an electronic oscillator, such as a voltage-controlled oscillator (VCO), are disclosed. In one aspect, an...
US-9,450,590 Clock distribution network for multi-frequency multi-processor systems
Embodiments of a synchronous digital system are disclosed that may include generation of clock and synchronization signals. Any of a plurality of available...
US-9,450,589 Clock generation system with dynamic distribution bypass mode
In some embodiments, a tight loop mode is provided is which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency...
US-9,450,588 Phase lock loop, voltage controlled oscillator of the phase lock loop, and method of operating the voltage...
A voltage controlled oscillator (VCO) includes a sensing circuit, where the sensing circuit is configured to generate a plurality of compensation control...
US-9,450,587 Test circuit and test method of semiconductor apparatus
A test circuit of a semiconductor apparatus may include a period signal counting block configured to count a period signal by a predetermined number of times,...
US-9,450,586 Security shield assembly
A security shield assembly has a printed circuit board having a plurality of layers, the plurality of layers including an electrically conductive penetration...
US-9,450,585 Selecting four signals from sixteen inputs
An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1...
US-9,450,584 Semiconductor device
A semiconductor device includes a first circuit applying an enable signal having a first logic level and a clock signal having the first logic level, supplying...
US-9,450,583 Input/output circuit with high voltage tolerance and associated apparatus
An input/output (IO) circuit with high voltage tolerance is provided. In an integrated circuit, the IO circuit includes a charge pump for generating a bias...
US-9,450,582 Programmable buffer system
A programmable buffer system includes a plurality of programmable resources. Each of the programmable resources includes, in an unconfigured state, a buffer...
US-9,450,581 Logic circuit, semiconductor device, electronic component, and electronic device
A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is...
US-9,450,580 Digital power gating with programmable control parameter
An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores...
US-9,450,579 Radio frequency devices having reduced intermodulation distortion
Radio-frequency (RF) devices are disclosed providing reduced intermodulation distortion. Disclosed RF and semiconductor devices can include a semiconductor...
US-9,450,578 Integrated clock gater (ICG) using clock cascode complimentary switch logic
Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance...
US-9,450,577 Circuit with output switch
An output circuit includes: an output switch including a gate terminal, a drain terminal coupled to an external I/O bus, and a well terminal; a well control...
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