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Patent # Description
US-9,449,970 Semiconductor devices and methods of forming the same
A semiconductor device includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction...
US-9,449,969 Device and method for a high isolation switch
An embodiment integrated circuit includes a switch and a conductive line over the switch. The switch includes a gate, a first source/drain region at a top...
US-9,449,968 Method for manufacturing a semiconductor device and a semiconductor device
A semiconductor device is formed by forming: a transistor in a semiconductor substrate having a main surface; a source region and a drain region; and a channel...
US-9,449,967 Transistor array structure
A semiconductor circuit can include a plurality of arrays of transistors having differing characteristics and operating at low voltages and currents. A drain...
US-9,449,966 Three-dimensional semiconductor device and method of manufacturing the same
A three-dimensional (3D) semiconductor device is provided, comprising a substrate having a staircase region comprising N steps, wherein N is an integer one or...
US-9,449,964 Semiconductor process
A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first...
US-9,449,963 Gate structure with hard mask structure formed thereon and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first capacitor structure. The first capacitor...
US-9,449,962 N-well/P-well strap structures
Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating...
US-9,449,961 Panel device having electrostatic discharge protection
A display device includes a substrate, at least one signal circuit, a ground protection circuit, and an auxiliary protection circuit. The substrate has a first...
US-9,449,960 Electrostatic discharge protection structure
Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first...
US-9,449,959 ESD protection circuit cell
A device includes a first bidirectional PNP circuit coupled to a first output of an communication circuit, and a second bidirectional PNP circuit coupling to a...
US-9,449,958 Light-emitting diode device
A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the...
US-9,449,957 Control and driver circuits on a power quad flat no-lead (PQFN) leadframe
According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase and W-phase power switches situated on the PQFN leadframe...
US-9,449,956 Optical apparatus
An optical apparatus includes a substrate 1, a wiring pattern 8 formed on the substrate 1, a light-receiving element 3 and a light-emitting element 2 provided...
US-9,449,955 Optical module integrated package
A an optical module integrated package includes a substrate, a light-receiving chip mounted in a light-receiving region of the substrate, an electronic...
US-9,449,954 LED with IC integrated lighting module
The present disclosure involves a method of packaging light-emitting diodes (LEDs). A carrier having a first side and a second opposite the first side is...
US-9,449,953 Package-on-package assembly and method for manufacturing the same
A package-on-package (PoP) assembly includes a bottom die package and a top die package mounted on the bottom die package. The bottom die package includes an...
US-9,449,952 Accessing or interconnecting integrated circuits
Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and...
US-9,449,951 Semiconductor device
A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor...
US-9,449,950 Semiconductor device, related manufacturing method, and related electronic device
A semiconductor device may include the following elements: a first substrate; a second substrate; a dielectric layer, which may be positioned between the first...
US-9,449,949 Method for manufacturing semiconductor device and semiconductor device
A first semiconductor chip has a first electrode pad, and a second semiconductor chip has a first through via and a second electrode pad joined to the via and...
US-9,449,948 Chip support substrate, chip support method, three-dimensional integrated circuit, assembly device, and...
The present invention relates to a chip support substrate including a lyophilic region 4 that is formed on the substrate and that absorbs a chip 3A, and an...
US-9,449,947 Semiconductor package for thermal dissipation
A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using...
US-9,449,946 Semiconductor device and manufacturing method thereof
Disclosed are a semiconductor device and a manufacturing method thereof, which can achieve miniaturization and improvement in the integration level by forming a...
US-9,449,945 Filter and capacitor using redistribution layer and micro bump layer
An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above...
US-9,449,944 Electronic component package and method for manufacturing same
There is provided a method for manufacturing an electronic component package, wherein a first electronic component and a second electronic component are placed...
US-9,449,943 Semiconductor device and method of balancing surfaces of an embedded PCB unit with a dummy copper pattern
A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of...
US-9,449,942 Method of making RFID devices on fabrics by stitching metal wires
A method for making a Radio Frequency Identification (RFID) device on fabric is described herein. In a first example, an RFID semiconductor chip is attached to...
US-9,449,941 Connecting function chips to a package to form package-on-package
A package-on-package (PoP) comprises a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate...
US-9,449,940 Methods and structures for processing semiconductor devices using polymeric materials and adhesives
Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at...
US-9,449,939 Geometry of contact sites at brittle inorganic layers in electronic devices
An electronic device (10, 20, 30, 40) is provided which comprises a substrate (16) supporting an inorganic layer (11) and a joint (13), mechanically coupling a...
US-9,449,938 Conductive die attach film for large die semiconductor packages and compositions useful for the preparation thereof
Provided herein are conductive die attach films having advantageous properties for use in a variety of applications, e.g., for the preparation of large die...
US-9,449,937 Semiconductor device and method for manufacturing the same
There is provided a semiconductor device. The semiconductor device of the present invention includes a semiconductor element and a metal buffer layer in an...
US-9,449,936 Grid array connection device and method
A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as...
US-9,449,935 Wafer level package and fabrication method thereof
A semiconductor device includes a chip having an active surface and a rear surface that is opposite to the active surface; a molding compound covering and...
US-9,449,934 Solder joint structure for ball grid array in wafer level package
A semiconductor device package and a method for forming the same using an improved solder joint structure are disclosure. The package includes solder joints...
US-9,449,933 Packaging device and method of making the same
A device includes a first and a second package component. A metal trace is disposed on a surface of the first package component. The metal trace has a...
US-9,449,932 Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die
A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first...
US-9,449,931 Pillar bumps and process for making same
Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a...
US-9,449,930 Semiconductor devices and package substrates having pillars and semiconductor packages and package stack...
A semiconductor device, a semiconductor package, and a package stack structure include a semiconductor substrate, a first bonding pad disposed on a first...
US-9,449,929 Semiconductor device and layout design system
In a semiconductor device including a seal ring area containing multiple seal rings are coupled to each other at equal intervals via bridge patterns, improper...
US-9,449,928 Layer arrangement
A layer arrangement in accordance with various embodiments may include: a wafer; a passivation disposed over the wafer; a protection layer disposed over at...
US-9,449,927 Seal ring structure with metal-insulator-metal capacitor
A seal ring structure of an integrated circuit includes a seal ring and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a top electrode, a...
US-9,449,926 Semiconductor device
In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the...
US-9,449,925 Integrated passive devices
A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit...
US-9,449,924 Multilevel contact to a 3D memory array and method of making thereof
A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of...
US-9,449,923 Methods of forming substrate microvias with anchor structures
Methods of forming anchor structures in package substrate microvias are described. Those methods and structures may include forming a titanium layer in an...
US-9,449,922 Contact critical dimension control
In a method for manufacturing a semiconductor device, a dielectric layer is formed on a substrate, and a contact hole is formed from the dielectric layer to the...
US-9,449,921 Voidless contact metal structures
Voidless contact metal structures are provided. In one embodiment, a voidless contact metal structure is provided by first providing a first contact metal that...
US-9,449,920 Electronic device
An electronic device is disclosed. The electronic device comprises a transistor provided on a substrate, a transmission line provided on the substrate and...
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