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Patent # Description
US-9,449,919 Semiconductor device, layout design and method for manufacturing a semiconductor device
A semiconductor device includes a first interconnect structure. The first interconnect structure includes a first interconnect portion, a second interconnect...
US-9,449,918 Semiconductor device having fuse pattern
A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical...
US-9,449,917 Method of forming an inductor with magnetic material
In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the...
US-9,449,916 Radio-frequency integrated circuits including inductors and methods of fabricating the same
A radio-frequency integrated circuit (RFIC) includes a substrate, an N-type deep well region disposed in an upper region of the substrate and having a top...
US-9,449,915 Semiconductor device and method of manufacturing the same
Provided is a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a dielectric layer. The dielectric...
US-9,449,914 Stacked integrated circuits with redistribution lines
An integrated circuit structure includes a first and a second semiconductor chip. The first semiconductor chip includes a first substrate and a first plurality...
US-9,449,913 3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined...
A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs)...
US-9,449,912 Integrated circuit (IC) card having an IC module and reduced bond wire stress and method of forming
An integrated circuit (IC) module for an IC card includes a plurality of IC card contacts in side-by-side relation. A dielectric support layer is above the...
US-9,449,911 Fan-out wafer level package and manufacturing method thereof
Provided are a wafer level package and a manufacturing method thereof. The wafer level package method includes preparing a patterned wafer, forming a recess in...
US-9,449,910 Stress relief layout for high power semiconductor package
A semiconductor device according to the present invention includes: an insulating substrate; a circuit pattern having a first surface that is bonded to a first...
US-9,449,909 Method of forming a package substrate
In accordance with an embodiment, a method comprises providing a substrate having a conductive material thereon, forming a ground plane, a first trace rail, and...
US-9,449,908 Semiconductor package system and method
A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die...
US-9,449,907 Stacked semiconductor chips packaging
Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that...
US-9,449,906 Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming one or more...
US-9,449,905 Plated terminals with routing interconnections semiconductor device
A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of...
US-9,449,904 Semiconductor device
A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a...
US-9,449,903 Ball grid array package with improved thermal characteristics
An integrated circuit package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween and a semiconductor die...
US-9,449,902 Semiconductor packages having multiple lead frames and methods of formation thereof
In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead...
US-9,449,901 Lead frame with deflecting tie bar for IC package
A packaged integrated circuit (IC) device having a heatsink mounted onto an IC die, itself mounted onto a die pad, is assembled using a lead frame having tie...
US-9,449,900 Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
A support feature on a leadframe to support a semiconductor die during placement of the die on the leadframe and minimize the collapsing effect of the connector...
US-9,449,899 Semiconductor package with heat spreader
A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the...
US-9,449,898 Semiconductor device having backside interconnect structure through substrate via and method of forming the same
A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via...
US-9,449,897 Chip package and method for forming the same
An embodiment of the invention provides a chip package which includes: a semiconductor substrate; a device region formed in the semiconductor substrate; at...
US-9,449,896 Device comprising a three-dimensional integrated structure with simplified thermal dissipation, and...
A device includes a support, a three-dimensional integrated structure above the support, and a lateral encapsulation region arranged around the structure. The...
US-9,449,895 Cooling system for molded modules and corresponding manufacturing methods
A cooling system for molded modules includes a plurality of individual modules each including a semiconductor die encapsulated by a mold compound, a plurality...
US-9,449,894 Base with heat absorber and heat dissipating module having the base
An exemplary base includes a heat absorber and clips attached to the heat absorber. The heat absorber includes a top surface and a bottom surface. A pair of...
US-9,449,893 Semiconductor module
A semiconductor module includes a semiconductor chip having a switching function, a resin portion that covers the chip, terminals, and a heat dissipation...
US-9,449,892 Manufacturing method of magnetic memory device
According to one embodiment, a manufacturing method of a magnetic memory device, includes obtaining first and second magnetic fields for each of ...
US-9,449,891 Proximity switch fabrication method using angled deposition
A method involves applying a voltage to a first conductive surface and a second conductive surface separated by a conductive surface gap of a distance greater...
US-9,449,890 Methods for temporary bussing of semiconductor package substrates
Methods for temporary bussing of semiconductor package substrates are disclosed and may include metal plating regions of a packaging substrate utilizing a...
US-9,449,889 Method for monitoring ion implantation
A method comprises placing a wafer and a ring-shaped beam profiler on a wafer holder, wherein the ring-shaped beam profiler is adjacent to the wafer, moving a...
US-9,449,888 Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same
A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also...
US-9,449,887 Method of forming replacement gate PFET having TiALCO layer for improved NBTI performance
A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a workfunction metal layer...
US-9,449,886 Semiconductor device and formation thereof
A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow...
US-9,449,885 High germanium content FinFET devices having the same contact material for nFET and pFET devices
FinFET structures are formed on silicon germanium fins having high germanium content. Silicon germanium source/drain regions formed in fin recesses in nFET...
US-9,449,884 Semiconductor device with trench epitaxy and contact
A semiconductor device comprises a semiconductor fin arranged on a substrate, a gate stack arranged over a channel region of the fin, a spacer arranged in...
US-9,449,883 Semiconductor device and method for manufacturing the same
First protective films are formed to cover side surfaces of gate electrode portions. In an nMOS region, an extention implantation region is formed by causing a...
US-9,449,882 Semiconductor device and manufacturing method thereof
In manufacturing a semiconductor device, a stack of first and second semiconductor layers are formed. A fin structure is formed by patterning the first and...
US-9,449,881 Methods of forming fins for FinFET semiconductor devices and the resulting devices
A method includes forming a plurality of fins above a substrate, forming at least one dielectric material above and between the plurality of fins, and forming a...
US-9,449,880 Fin patterning methods for increased process margin
A method for fabricating a semiconductor device includes forming a plurality of first spacers over a substrate. A second spacer of a plurality of second spacers...
US-9,449,879 Method of severing a semiconductor device composite
A method of severing a semiconductor device composite includes a carrier having a main surface and a semiconductor layer sequence arranged on the main surface...
US-9,449,878 Wafer processing method
A wafer processing method includes a cut groove forming step of positioning, from a back side of the substrate, a cutting blade to an area corresponding to a...
US-9,449,877 Method of protecting a mounting tape during laser singulation of a wafer
A method of singulating a semiconductor wafer with laser energy while the semiconductor wafer is supported on a mounting tape during singulation comprises the...
US-9,449,876 Singulation of semiconductor dies with contact metallization by electrical discharge machining
A method of separating individual dies of a semiconductor wafer includes forming a metal layer on a first surface of a semiconductor wafer, the semiconductor...
US-9,449,875 Wafer backside interconnect structure connected to TSVs
An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor...
US-9,449,874 Self-forming barrier for subtractive copper
A method of forming electrically conductive structures that includes forming a copper containing layer including a barrier forming element, and applying a first...
US-9,449,873 Method for processing a carrier and an electronic component
In various embodiments, a method for processing a carrier is provided. The method for processing a carrier may include: forming a first catalytic metal layer...
US-9,449,872 Method for forming cobalt barrier layer and metal interconnection process
The present invention provides a method for forming a cobalt barrier layer and a metal interconnection process. The method is performed on a surface of a...
US-9,449,871 Hybrid airgap structure with oxide liner
A technique relates to an airgap structure. A dielectric layer is formed on an underlying layer. Copper filled trenches are formed in the dielectric layer, and...
US-9,449,870 Methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby
Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes...
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