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| Patent # | Description |
|---|---|
| US-9,449,869 |
Method for fabricating interconnect structure Various embodiments provide interconnect structures and fabrication methods. A carbon-containing dielectric layer can be formed on a substrate. A protective... |
| US-9,449,868 |
Methods of forming semiconductor diodes by aspect ratio trapping with
coalesced films A method of forming a photonic device that comprises a substrate and a dielectric material including two or more openings that expose a portion of the... |
| US-9,449,867 |
VHF etch barrier for semiconductor integrated microsystem The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated... |
| US-9,449,866 |
Methods and systems for using oxidation layers to improve device surface
uniformity The invention discloses a treatment process for a semiconductor, comprising providing a substrate, the substrate comprises silicon material; defining a trench... |
| US-9,449,865 |
Electrostatic clamp, lithographic apparatus and method The present invention provides a method for containing unwanted electric charge that accumulates on the surface of the dielectric of an electrostatic clamp. One... |
| US-9,449,864 |
Systems and methods for fabricating and orienting semiconductor wafers A system for orienting a semiconductor wafer. The system includes a wafer retaining device configured to retain a semiconductor wafer, a light source configured... |
| US-9,449,863 |
Device for aligning and pre-fixing a wafer A device for aligning and prefixing a flat substrate on a carrier substrate for the further processing of the substrate. The device includes aligning means for... |
| US-9,449,862 |
Parallel single substrate processing system A system for processing surfaces of substrates having a process module having a process module frame and a plurality of process elements to process the... |
| US-9,449,861 |
Substrate processing apparatus An object of the present invention is to provide a technique capable of reducing a volume occupied exclusively by a substrate processing apparatus. In order to... |
| US-9,449,859 |
Multi-gas centrally cooled showerhead design A method and apparatus for chemical vapor deposition and/or hydride vapor phase epitaxial deposition are provided. The apparatus generally include a lower... |
| US-9,449,858 |
Transparent reflector plate for rapid thermal processing chamber The present invention generally relates to methods and apparatus for processing substrates. Embodiments of the invention include apparatuses for processing a... |
| US-9,449,857 |
Substrate processing apparatus and substrate processing method A substrate processing apparatus is provided including: a liquid processing unit that processes a substrate with a processing liquid; a carry-in port formed in... |
| US-9,449,856 |
Encapsulant with base for use in semiconductor encapsulation,
semiconductor apparatus, and method for... The present invention provides an encapsulant with a base for use in semiconductor encapsulation, for collectively encapsulating a device mounting surface of a... |
| US-9,449,855 |
Double-etch nanowire process In an aspect of this disclosure, a method is provided comprising the steps of: (a) providing a silicon-containing substrate, (b) depositing a first metal on the... |
| US-9,449,854 |
Semiconductor device and method of manufacturing the same Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a... |
| US-9,449,853 |
Method for manufacturing semiconductor device comprising electron trap
layer A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically... |
| US-9,449,852 |
Method for manufacturing semiconductor device A semiconductor device including an oxide semiconductor with stable electric characteristics and high reliability is provided. An island-shaped oxide... |
| US-9,449,851 |
Local doping of two-dimensional materials This disclosure provides systems, methods, and apparatus related to locally doping two-dimensional (2D) materials. In one aspect, an assembly including a... |
| US-9,449,850 |
Processing systems and methods for halide scavenging Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for... |
| US-9,449,849 |
Method of manufacturing semiconductor device using meander-shaped heating
element Provided is a method of manufacturing a semiconductor device using a heating device capable of suppressing shearing of a holder due to thermal deformation of... |
| US-9,449,848 |
Manufacturing method for semiconductor device, annealing device, and
annealing method According to one embodiment, the manufacturing method for the semiconductor device according to the embodiment includes carrying out ion implantation to the... |
| US-9,449,847 |
Method for manufacturing a semiconductor device by thermal treatment with
hydrogen A semiconductor device is manufactured by forming semiconductor elements extending between a front surface and a rear side of a semiconductor layer. This... |
| US-9,449,846 |
Vertical gate separation Methods of selectively etching tungsten from the surface of a patterned substrate are described. The methods electrically separate vertically arranged tungsten... |
| US-9,449,845 |
Selective titanium nitride etching Methods of etching exposed titanium nitride with respect to other materials on patterned heterogeneous structures are described, and may include a remote plasma... |
| US-9,449,844 |
Etching method, etching apparatus, and storage medium An etching method for anisotropically etching a Cu film on a substrate surface includes providing a substrate having a Cu film on a surface thereof in a chamber... |
| US-9,449,843 |
Selectively etching metals and metal nitrides conformally Methods of selectively etching metals and metal nitrides from the surface of a substrate are described. The etch selectively removes metals and metal nitrides... |
| US-9,449,842 |
Plasma etching method A plasma etching method for plasma etching a film to be etched to a size smaller than a prescribed size using a mask patterned to the prescribed size performs... |
| US-9,449,841 |
Methods and systems for chemical mechanical polish and clean The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor structure including a metal gate... |
| US-9,449,840 |
Methods of forming different sized patterns A method includes forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on... |
| US-9,449,839 |
Self-assembled monolayer for pattern formation The present disclosure relates to a method of forming a pattern on a semiconductor substrate. One or more layers are formed over the semiconductor substrate. A... |
| US-9,449,838 |
Semiconductor device manufacturing method In a semiconductor device manufacturing method, a target object including a multilayer film and a mask formed on the multilayer film is prepared in a processing... |
| US-9,449,837 |
3D chip-on-wafer-on-substrate structure with via last process Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second... |
| US-9,449,836 |
Method for forming features with sub-lithographic pitch using directed
self-assembly of polymer blend There is provided a manufacturing method of a semiconductor device including forming a first pattern of first features, according to a lithography process, in a... |
| US-9,449,835 |
Methods of forming features having differing pitch spacing and critical
dimensions Methods of forming features having differing pitch spacing and critical dimensions are disclosed herein. One method includes forming an underlying layer of... |
| US-9,449,834 |
Method of fabricating semiconductor devices including PMOS devices having
embedded SiGe A method of fabricating semiconductor device is provided. First, a recess having a substantially rectangular cross section is formed in a substrate. Then, oxide... |
| US-9,449,833 |
Methods of fabricating self-aligned FETS using multiple sidewall spacers A self-aligned process for locating a stem of a T-shaped gate relative to source and drain contacts of a FET or HEMT. The gate stem is located asymmetrically in... |
| US-9,449,832 |
Metal gate structure A method comprises depositing a metal layer partially filling a trench of a gate structure, forming a protection layer on the metal layer, wherein a sidewall... |
| US-9,449,831 |
Oxide-nitride-oxide stack having multiple oxynitride layers An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device... |
| US-9,449,830 |
Transistor having tungsten-based buried gate structure, method for
fabricating the same A method for fabricating a transistor that includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a first... |
| US-9,449,829 |
Semiconductor process A semiconductor process includes the following steps. A dielectric layer is formed on a substrate. A barrier layer is formed on the dielectric layer. An ammonia... |
| US-9,449,828 |
Method of forming metal gate electrode An aspect of this description relates to a method that includes partially filling an opening in a dielectric material with a high-dielectric-constant material.... |
| US-9,449,827 |
Metal semiconductor alloy contact resistance improvement Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. A first transition metal liner including at... |
| US-9,449,826 |
Graded well implantation for asymmetric transistors having reduced gate
electrode pitches In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a... |
| US-9,449,825 |
Heat treatment apparatus for heating substrate by irradiation with flashes
of light, and heat treatment method A first flash heating is performed in which a lower flash lamp irradiates a back surface of a semiconductor wafer with flashes of light, so that heat conduction... |
| US-9,449,824 |
Method for patterned doping of a semiconductor A method for an improved doping process allows for improved control of doping concentrations on a substrate. The method may comprise printing a polymeric... |
| US-9,449,823 |
Method for manufacturing silicon carbide semiconductor device In a state where a silicon carbide substrate having a first main surface and second main surface opposite to each other is fixed to a base material having a... |
| US-9,449,822 |
Method of forming semiconductor structures with contact holes Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes forming a set of shapes on top of a substrate;... |
| US-9,449,821 |
Composite hard mask etching profile for preventing pattern collapse in
high-aspect-ratio trenches High-aspect ratio trenches in integrated circuits are fabricated of composite materials and with trench boundaries having pencil-like etching profiles. The... |
| US-9,449,820 |
Epitaxial growth techniques for reducing nanowire dimension and pitch Techniques for reducing nanowire dimension and pitch are provided. In one aspect, a pitch multiplication method for nanowires includes the steps of: providing... |
| US-9,449,819 |
Semiconductor device A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The... |
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