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Patent # Description
US-9,449,718 Method for setting a flash memory for HTOL testing
A method for setting voltages in a flash memory for high temperature operating life (HTOL) testing is provided. The flash memory includes a substrate, a source,...
US-9,449,717 Memory built-in self-test for a data processing apparatus
A data processing apparatus has at least one memory and processing circuitry. A memory built-in self-test (MBIST) interface receives a MBIST request indicating...
US-9,449,716 Circuit board having bypass pad
An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be...
US-9,449,715 Semiconductor device having capability of generating chip identification information
A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in...
US-9,449,714 Flexible interrupt generation mechanism
In a testing device, a method for implementing efficient interrupt routing. The method includes receiving an interrupt from a plurality of interrupt causes,...
US-9,449,713 Method for preconditioning thin film storage array for data retention
A method includes over-programming thin film storage (TFS) memory cells on a semiconductor wafer with a first voltage that is higher than a highest voltage used...
US-9,449,712 Shift register with higher driving voltage of output stage transistor and flat panel display using the same
A shift register and flat panel display using the same is provided therein. The shift register receives an operating voltage level. Through the circuit provided...
US-9,449,711 Shift register circuit and shading waveform generating method
A shift register circuit and a shading waveform generating method are disclosed. The shift register circuit includes plural stages of shift registers. Each...
US-9,449,710 Decoding and scan driver
The present invention relates to a decoding and scan driver, which comprises a level-shift circuit, a decoding circuit, an output driving circuit, and a control...
US-9,449,709 Volatile memory and one-time program (OTP) compatible memory cell and programming method
A volatile and one-time program (OTP) compatible asymmetric memory cell may include a first pull-up transistor having a first threshold voltage. The asymmetric...
US-9,449,708 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array configured having NAND strings arranged therein; a plurality...
US-9,449,707 Systems and methods to mitigate program gate disturb in split-gate flash cell arrays
A memory circuit has control gate circuitry (104) and select gate circuitry (106). A first memory cell (122/124) has a control gate coupled to the control gate...
US-9,449,706 Driving method for a semiconductor device with an oxide semiconductor layer between two gate electrodes
A memory device in which data can be retained for a long time is provided. The memory device includes a memory element and a transistor which functions as a...
US-9,449,705 Programming schemes for multi-level analog memory cells
A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume...
US-9,449,704 Flexible clock scheme of flash memory, memory module, computer-readable recording medium and operating method...
A flash memory, a memory module, a computer-readable recording medium and an operating method are provided, which can perform a flexible setup by a flexible...
US-9,449,703 Systems and methods for driving a control gate with a select gate signal in a split-gate nonvolatile memory cell
A nonvolatile memory includes a memory array having a plurality of memory cells, a select gate driver configured to provide a select gate voltage to a select...
US-9,449,702 Power management
According to an embodiment of the invention there may be provided a method for measuring, by a power measurement circuit of a memory controller, a power...
US-9,449,701 Non-volatile storage systems and methods
A non-volatile storage system is provided. The non-volatile storage system includes a memory array that includes a plurality of bit lines and a plurality of...
US-9,449,700 Boundary word line search and open block read methods with reduced read disturb
Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last...
US-9,449,699 Nonvolatile memory and erasing method thereof
An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with...
US-9,449,698 Block and zone erase algorithm for memory
Techniques are provided for erasing a memory device. In one aspect, different zones of a block can be separately erased and subject to a verify test. Erase...
US-9,449,697 Semiconductor memory device and manufacturing method thereof
A semiconductor memory device is provided, which can suppress current leakage generated during a programming action so that the programming action can be...
US-9,449,696 Direct-transfer marching memory and a computer system using the same
A direct-transfer marching memory includes an array of memory units, each of the memory units having a sequence of bit-level cells so as to store information of...
US-9,449,695 Nonvolatile memory system including nonvolatile memory device and memory controller and operating method of...
A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells, and a memory controller. The memory controller is...
US-9,449,694 Non-volatile memory with multi-word line select for defect detection operations
A stress mode for use in testing non-volatile memory arrays for a number of types of defects is described. More specifically, a multi-word line select option...
US-9,449,693 Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and...
A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a...
US-9,449,692 Functional data programming and reading in a memory
Methods for functional programming memory cells and apparatuses are disclosed. One such method for functional programming includes encoding a group of data with...
US-9,449,691 Memory device including memory blocks and decoders to output memory block selection signals
A memory device includes a plurality of memory blocks, and a row decoder including a plurality of decoders including a first decoder and a second decoder, the...
US-9,449,690 Modified local segmented self-boosting of memory cell channels
A method of programming a memory system by selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed. A...
US-9,449,689 Semiconductor memory device
A semiconductor memory device includes a string of memory cell transistors that are connected to each other in series. A selection transistor is connected...
US-9,449,688 Device and method for writing data to a resistive memory
The invention relates to a resistive memory including resistive elements, the resistance of each resistive element being capable of alternating between a high...
US-9,449,687 Sense circuits, memory devices, and related methods for resistance variable memory
Sense circuits, memory devices, and related methods are disclosed. A sense circuit includes sample and hold circuitry configured to sample and hold a second...
US-9,449,686 Resistive memory device, resistive memory system and method of operating the resistive memory device
A method of operating a resistive memory device and a resistive memory system including a resistive memory device is for a resistive memory device including a...
US-9,449,685 Resistance variable memory apparatus, read circuit unit and operation method therefor
A resistance variable memory apparatus may include: a memory cell array; and a read circuit unit configured to receive a cell current, generate a digital code...
US-9,449,684 Storage control device, storage device, information processing system, and storage control method
Provided is a storage control device including: a detection unit which detects a first timing for performing a first rewriting process of performing only a...
US-9,449,683 Memory cells having a plurality of resistance variable materials
Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an...
US-9,449,682 Reading a multi-bit value from a memory cell
Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In...
US-9,449,681 Pre-charging a data line
A circuit includes a signal generating circuit that generates a pre-charge signal based on a clock signal and a column select signal for a column of memory...
US-9,449,680 Write assist circuit and memory cell
A write assist circuit capable of writing data to a memory cell with a bit line and a bit line bar is provided. The write assist circuit includes a clamping...
US-9,449,679 Memory devices and control methods thereof
A memory device includes a first signal line; a memory cell array divided into a first area and a second area and having a plurality of first memory cells and...
US-9,449,678 Semiconductor integrated circuit device
A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an...
US-9,449,677 Methods of operating and forming semiconductor devices including dual-gate electrode structures
A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and...
US-9,449,676 Driver circuit
A method of operation in a memory controller includes operating pull-up and pull-down drivers driven by separate pre-drivers between different voltage rails....
US-9,449,675 Apparatuses and methods for identifying an extremum value stored in an array of memory cells
The present disclosure includes apparatuses and methods related to identifying an extremum value using sensing circuitry. An example method can include...
US-9,449,674 Performing logical operations using sensing circuitry
Apparatuses and methods related to performing logical operations using sensing circuitry are disclosed. One apparatus comprises an array of memory cells,...
US-9,449,673 Memory device and memory system having the same
A memory device includes a memory cell array, a multi-purpose register (MPR) and a control unit. The memory cell array includes a plurality of memory blocks....
US-9,449,672 DRAM memory interface
It is proposed a DRAM memory interface (40) for transmitting signals between a memory controller device (50) and a DRAM memory device (52). The DRAM memory...
US-9,449,671 Techniques for probabilistic dynamic random access memory row repair
Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum...
US-9,449,670 Bit-line sense amplifier, semiconductor memory device and memory system including the same
A semiconductor memory device is provided which includes a sense amplifier, a bit line connected to a plurality of memory cells of a first memory block, a...
US-9,449,669 Cross-coupled thyristor SRAM circuits and methods of operation
A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or...
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