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Patent # Description
US-9,448,963 Low-power reconfigurable architecture for simultaneous implementation of distinct communication standards
A chip architecture for use in processing signals encoded in accordance with any one of a plurality of communication protocols each defined by a series of...
US-9,448,962 User experience/user interface based on interaction history
In one embodiment, a method includes determining, relative to a base user experience (UX), one or more modifications to one or more graphical elements of a user...
US-9,448,961 Prioritized download of social network content
A computer-implemented method includes identifying, with a computer system that has a network interface, one or more primary categories of content from a social...
US-9,448,960 Address translation in I2C data communications system
A novel readdressing circuit is provided for supporting data communications over a data line and a clock line between at least one master device and multiple...
US-9,448,959 Two-wire communication protocol engine
In an example embodiment, a two-wire communication protocol engine manages control and data transmissions in a bi-directional, multi-node bus system where each...
US-9,448,958 Network resource management system utilizing physical network identification for bridging operations
The disclosed network resource management system employs a hardware configuration management (HCM) information handling system (IHS) that may couple to a single...
US-9,448,957 Unified system area network and switch
A network switch, based on the PCI Express protocol, is disclosed. The switch includes a processor, local memory and a plurality of non-transparent bridges. By...
US-9,448,956 Stuffing bits on a memory bus between data bursts
According to some embodiments, a method and apparatus are provided to receive a first data burst associated with a first data line and a second data burst...
US-9,448,955 Method for controlling interruption in data transmission process
A method of controlling interrupts in the process of data transmission used for transmitting data between an information processing device and a storage device...
US-9,448,954 Method and an apparatus for coherency control
The subject matter discloses a method for data coherency; the method comprising receiving an interrupt request for interrupting a CPU; wherein the interrupt...
US-9,448,953 Memory subsystem and computer system
The present invention provides a computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other. The computer...
US-9,448,952 Apparatus and method for synchronizing dynamic process data across redundant input/output modules
A method includes receiving first data at a first I/O module from a second I/O module, where the first data defines a programmable device configuration. The...
US-9,448,951 Processor communications
A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral...
US-9,448,950 Using authenticated manifests to enable external certification of multi-processor platforms
Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected...
US-9,448,949 Mobile data vault
A portable electronic device is provided. The portable electronic device includes a data interface module that processes files associated with a user, the data...
US-9,448,948 Efficient replica cleanup during resynchronization
Mechanisms are provided for efficient replica cleanup during resynchronization. According to various embodiments, a plurality of deleted data segment ranges on...
US-9,448,947 Inter-chip memory interface structure
In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each...
US-9,448,946 Data storage system with stale data mechanism and method of operation thereof
Systems, methods and/or devices are used to enable a stale data mechanism. In one aspect, the method includes (1) receiving a write command specifying a logical...
US-9,448,945 Using a decrementer interrupt to start long-running hardware operations before the end of a shared processor...
Method to perform an operation, the operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle,...
US-9,448,944 Method and system for dynamic templatized query language in software
A system to automatically generate query language in software is described. The system receives a request for data that is persistently stored in a database....
US-9,448,943 Partial volume access in a physical stacked volume
A computer-implemented method for accessing data stored in a virtual tape storage (VTS) system, according to one embodiment, include receiving a mount request...
US-9,448,942 Random access of a cache portion using an access module
A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the...
US-9,448,941 System and method for cache management
A method, computer program product, and computing system for processing one or more data chunks on a host server. The one or more data chunks are destined for...
US-9,448,940 Multiple core computer processor with globally-accessible local memories
A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of...
US-9,448,939 Collecting memory operand access characteristics during transactional execution
A transactional execution of a set of instructions in a transaction of a program may be initiated to collect memory operand access characteristics of a set of...
US-9,448,938 Cache coherence protocol for persistent memories
A memory device having a memory controller, a main memory with at least a portion comprising persistent memory, and at least two processing entities, wherein...
US-9,448,937 Cache coherency
A system is disclosed that includes a memory, a processing sub-system, and a programmable logic sub-system. The processing and programmable logic sub-systems...
US-9,448,936 Concurrent store and load operations
Systems, processors, and methods for efficiently handling concurrent store and load operations within a processor. A processor comprises a load-store unit (LSU)...
US-9,448,935 Surface resource view hash for coherent cache operations in texture processing hardware
Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a...
US-9,448,934 Affinity group access to global data
A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method...
US-9,448,933 Using redundant transactions to verify the correctness of program code execution
In the described embodiments, a processor core (e.g., a GPU core) receives a section of program code to be executed in a transaction from another entity in a...
US-9,448,932 System for caching data
A system for caching data in a distributed data processing system allows for the caching of user-modifiable data (as well as other types of data) across one or...
US-9,448,931 Endian conversion method and system
An endian conversion method is executed by a CPU, and includes executing a program that includes endian conversion setting; and performing, when accessing an...
US-9,448,930 Memory heaps in a memory model for a unified computing system
A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for...
US-9,448,929 Memory allocation folding based on object dominance
A computer-implemented method for compilation of applications can include receiving a set of software instructions and traversing the set of software...
US-9,448,928 System and method for two-tier adaptive heap management in a virtual machine environment
In accordance with an embodiment, described herein is a system and method for two-tier adaptive heap management (AHM) in a virtual machine environment, such as...
US-9,448,927 System and methods for removing obsolete data in a distributed system of hybrid storage and compute nodes
A distributed garbage collection in a distributed storage system is described, where the storage controller functions of the distributed storage system are...
US-9,448,926 Bidirectional counter in a flash memory
A method of storing a counter in at least two non-volatile memory pages, including: a step of initializing a page with an initial value and then, on each update...
US-9,448,925 Semiconductor storage device and semiconductor storage device control method
A semiconductor storage device includes: a storage; an address translater configured to translate a logical address for access to the storage to a physical...
US-9,448,924 Flash optimized, log-structured layer of a file system
In one embodiment, storage arrays of solid state drives (SSDs) coupled to a node are organized as redundant array of independent disks (RAID) groups. Each...
US-9,448,923 Information processing device for synchronizing update information between a solid state drive and a backup storage
An information processing device includes: an SSD storage controlling unit for storing a physical address of a storage region of data stored in an SSD (Solid...
US-9,448,922 High-performance storage structures and systems featuring multiple non-volatile memories
A memory storage system that includes at least a storage controller, a first non-volatile, solid-state memory and a second non-volatile, solid-state memory. The...
US-9,448,921 Page allocation for flash memories
Technologies are described herein for allocating pages in a flash memory. Some example technologies may receive multiple data elements and a write request to...
US-9,448,920 Granting and revoking supplemental memory allocation requests
Provided are a computer program product, system, and method for granting and revoking supplemental memory allocation requests. Supplemental memory allocations...
US-9,448,919 Data storage device accessing garbage collected memory segments
A data storage device is disclosed comprising a non-volatile memory comprising a plurality of memory segments. A first write command is received from a host...
US-9,448,918 Content-aware digital media storage device and methods of using the same
A content-aware digital media storage device includes a host device interface for exchanging digital information with a host device, a memory array for storing...
US-9,448,917 System on chip and verification method thereof
A verification method of a system on chip includes receiving a test generator and an exception handler; generating, by the test generator, a test program...
US-9,448,916 Software test automation systems and methods
Described are a system and method for performing an automated quality assessment on a software program under test. A test automation system executes a test on a...
US-9,448,915 Modular script designer for next generation testing system
A method for modular script design includes receiving, at a modular script designer component, script information from a user, generating a list of suggested...
US-9,448,914 Method and system for implementing remote debugging
The present disclosure discloses a method and a system for implementing remote debugging, and relates to the field of communications technologies. The disclosed...
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