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Patent # Description
US-9,455,278 Thin film transistor array panel and method of manufacturing the panel
A thin film transistor array panel includes: a gate line disposed on a substrate and including a first connection member of a gate driver region and a gate...
US-9,455,277 Array substrate, display panel and display device
An array substrate includes a substrate, a plurality of gate lines and a plurality of data lines intersecting each other and being insulating from each other,...
US-9,455,276 Thin film transistor array panel and method of manufacturing the same
A thin film transistor array panel includes: a substrate; a gate line and a common voltage line on the substrate and electrically separated from each other; a...
US-9,455,275 High voltage semiconductor devices
In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is...
US-9,455,274 Replacement fin process in SSOI wafer
A method of forming replacement fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and...
US-9,455,273 Semiconductor device
In a semiconductor device having an SRAM memory cell, its reliability is improved. In the semiconductor device having the SRAM memory cell, ...
US-9,455,272 Semiconductor device and method of manufacturing the same
A semiconductor device includes stacked groups each including interlayer insulating patterns and conductive patterns and stacked in at least two tiers, wherein...
US-9,455,271 Semiconductor memory device and method of manufacturing semiconductor memory device and method of layouting...
According to one embodiment, a semiconductor memory device includes a semiconductor substrate, which includes thereon a first region where memory elements are...
US-9,455,270 Semiconductor structure and manufacturing method of the same
A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate having a trench, a stacked...
US-9,455,269 Semiconductor memory device
A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including: a conductive layer, an inter-layer...
US-9,455,268 Staircase-shaped connection structures of three-dimensional semiconductor devices
Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the...
US-9,455,267 Three dimensional NAND device having nonlinear control gate electrodes and method of making thereof
A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate in...
US-9,455,266 Memory array with a pair of memory-cell strings to a single conductive pillar
An array of memory cells has a conductive pillar and a plurality of first and second memory cells coupled in series by the conductive pillar. Each first memory...
US-9,455,265 Semiconductor 3D stacked structure and manufacturing method of the same
A semiconductor structure is provided. The semiconductor structure includes a first stacked structure. The first stacked structure includes a first stacked...
US-9,455,264 Semiconductor device and manufacturing method thereof
A semiconductor device with a nonvolatile memory is provided which has improved electric performance. A memory gate electrode is formed over a semiconductor...
US-9,455,263 Three dimensional NAND device with channel contacting conductive source line and method of making thereof
A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first...
US-9,455,262 Semiconductor device having electrically floating body transistor, semiconductor device having both volatile...
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in...
US-9,455,261 Integrated structures
Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within...
US-9,455,260 Methods and structures for multiport memory devices
A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the...
US-9,455,259 Semiconductor devices including diffusion barriers with high electronegativity metals
A semiconductor device includes a capacitor with reduced oxygen defects at an interface between a dielectric layer and an electrode of the capacitor. The...
US-9,455,258 Semiconductor device and method of designing the same
A semiconductor device includes: a semiconductor substrate having a memory cell array region and a peripheral circuit region; a ferroelectric capacitor formed...
US-9,455,257 Semiconductor memory device and method of manufacturing the same
A connection unit is provided adjacently to the cell array unit and electrically connected to a peripheral circuit unit positioned downwardly of the cell array...
US-9,455,256 Inverter including two-dimensional material, method of manufacturing the same and logic device including inverter
Inverters including two-dimensional (2D) material, methods of manufacturing the same, and logic devices including the inverters. An inverter may include a first...
US-9,455,255 Fin-type field effect transistor and manufacturing method thereof
A method of manufacturing a fin-type field effect transistor includes sequentially forming a first mask and a second mask on a semiconductor substrate;...
US-9,455,254 Methods of forming a combined gate and source/drain contact structure and the resulting device
One method disclosed herein includes, among other things, forming a gate cap layer above a recessed final gate structure and above recessed sidewall spacers,...
US-9,455,253 Bidirectional switch
A bidirectional switch formed in a substrate includes first and second main vertical thyristors in antiparallel connection. A third auxiliary vertical thyristor...
US-9,455,252 Combining ZTCR resistor with laser anneal for high performance PMOS transistor
An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with...
US-9,455,251 Decoupling capacitor using finFET topology
Embodiments herein describe a decoupling capacitor that may include multiple fin and gate structures electrically insulated from a conductor (e.g., a metal...
US-9,455,250 Distributed decoupling capacitor
An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one...
US-9,455,249 Planar srfet using no additional masks and layout method
A semiconductor power device is supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an...
US-9,455,248 Semiconductor device with schottky diode and manufacturing method thereof
A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include:...
US-9,455,247 High-performance device for protection from electrostatic discharge
A semiconductor device for protection from electrostatic discharge includes a number of modules for protection from electrostatic discharge. Each module...
US-9,455,246 Fin diode structure
A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in...
US-9,455,245 Semiconductor device and a method for manufacturing semiconductor device
A semiconductor device is provided with a base member having a front surface and a plurality of semiconductor chips provided on the front surface and each...
US-9,455,244 Semiconductor package
A semiconductor package includes a package substrate. A first semiconductor chip is mounted on the package substrate. The first semiconductor chip includes a...
US-9,455,243 Silicon interposer and fabrication method thereof
A silicon interposer includes a silicon substrate having a front side and a rear side opposite to the front side; a first integrated circuit chip disposed in...
US-9,455,242 Semiconductor optoelectronic device
A semiconductor optoelectronic device comprises a growth substrate; a semiconductor epitaxial stack formed on the growth substrate comprising a sacrificial...
US-9,455,241 Integrated circuit package and method of forming the same
Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip...
US-9,455,240 Method of manufacturing semiconductor device and semiconductor device
Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape...
US-9,455,239 Integrated circuit chip and fabrication method
An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front...
US-9,455,238 Power converter
A power converter includes a bus bar, a semiconductor device, a lead, and solder. The bus bar has a vertical wall. The semiconductor device includes an...
US-9,455,237 Bowl-shaped solder structure
An apparatus relating generally to a substrate is disclosed. In this apparatus, a first metal layer is on the substrate. The first metal layer has an opening....
US-9,455,236 Integrated circuit packages and methods of forming same
Integrated circuit (IC) packages and methods of forming the IC packages are provided. In an embodiment, IC dies are formed and are placed on a carrier to form a...
US-9,455,235 Thin embedded packages, methods of fabricating the same, electronic systems including the same, and memory...
An embedded package includes a core layer having a cavity, a first semiconductor chip disposed in the cavity, and bumps disposed on a top surface of the first...
US-9,455,234 Fixture to constrain laminate and method of assembly
A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip...
US-9,455,233 System for preventing tampering with integrated circuit
A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes both a static wire mesh...
US-9,455,232 Semiconductor structure including a die seal leakage detection material, method for the formation thereof and...
A semiconductor structure includes a semiconductor substrate, one or more interconnect layers provided over the substrate and a circuit. The circuit includes a...
US-9,455,231 Resin-sealed semiconductor device and method of manufacturing the same
A resin-sealed semiconductor device includes a mesa-type semiconductor element which includes a mesa-type semiconductor base body having a pn junction exposure...
US-9,455,230 Semiconductor packages and methods of fabricating the same
A semiconductor package includes a semiconductor chip electrically connected to a substrate, and a molding part including first molding members and second...
US-9,455,229 Composite substrate manufacturing method, semiconductor element manufacturing method, composite substrate, and...
Provided is a composite substrate manufacturing method, including at least: a first raw board deforming step of preparing a first substrate by deforming a first...
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