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Patent # Description
US-9,455,228 Self-shielded components and methods for making the same
This is directed to self-shielded components and methods for making the same. A self-shielded component can include an electromagnetic interference (EMI) shield...
US-9,455,227 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the...
US-9,455,226 Semiconductor device allowing metal layer routing formed directly under metal pad
The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad...
US-9,455,225 Semiconductor device
To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same...
US-9,455,224 Semiconductor interconnect structures
Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some...
US-9,455,223 Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer...
A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The...
US-9,455,222 IC having failsafe fuse on field dielectric
A fuse circuit includes a substrate, a top semiconductor layer doped a first conductivity type having a well doped a second conductivity type formed therein...
US-9,455,221 Preparation method of three-dimensional integrated inductor-capacitor structure
The invention relates to a field of semiconductor manufacturing technology, more particularly, to a method for preparing three-dimensional integrated...
US-9,455,220 Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage...
A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric...
US-9,455,219 Wiring substrate and method of manufacturing the same
A wiring substrate includes, a base wiring substrate including a first wiring layer, a first insulating layer in which the first wiring layer is buried and a...
US-9,455,218 Embedded die-down package-on-package device
An apparatus including a die; and a build-up carrier including alternating layers of conductive material and dielectric material disposed on a device side of...
US-9,455,217 Semiconductor package including multiple chips and separate groups of leads
Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are...
US-9,455,216 Semiconductor device package and method of manufacture
A structure to improve saw singulation quality and wettability of integrated circuit packages (140) is assembled with lead frames (112) having half-etched...
US-9,455,215 Semiconductor device and method for manufacturing the same
A semiconductor device includes a conductive portion having semiconductor elements provided on a substrate, a case housing the conductive portion, and a lead...
US-9,455,214 Wafer frontside-backside through silicon via
A wafer frontside-backside through silicon via and methods of manufacture are disclosed. The method includes forming a plurality of frontside metalized vias...
US-9,455,213 Architecture for gas cooled parallel microchannel array cooler
Effective utilization of a parallel flow air-cooled microchannel array at the micro electro mechanical systems (MEMS) scale is prohibited by unfavorable flow...
US-9,455,212 Loop heat pipe system and information processing apparatus
A loop heat pipe system includes a loop heat pipe (LHP), a temperature sensor, a heater and a controller. The temperature sensor measures temperature of a...
US-9,455,211 Integrated fan-out structure with openings in buffer layer
A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer...
US-9,455,210 Curable composition
Provided are a curable composition and its use. The curable composition can exhibit excellent processibility and workability. The curable composition exhibits...
US-9,455,209 Circuit module and production method therefor
A circuit module includes: a wiring substrate including a mounting surface having first and second areas and a terminal surface on the other side of the...
US-9,455,208 Semiconductor device
An insertion vertical electrode region and part of a case-contact horizontal electrode region of an electrode insertion part of an external electrode is...
US-9,455,207 All-in-one power semiconductor module
Disclosed herein is an all-in-one power semiconductor module including a plurality of first semiconductor devices formed on a substrate; a housing molded and...
US-9,455,206 Overlay measuring method and system, and method of manufacturing semiconductor device using the same
An overlay measuring method includes irradiating an electron beam onto a sample, including a multi-layered structure of overlapped upper and lower patterns...
US-9,455,205 Semiconductor devices and processing methods
A method for processing a semiconductor device in accordance with various embodiments may include: providing a semiconductor device having a first pad and a...
US-9,455,204 10 nm alternative N/P doped fin for SSRW scheme
A method of introducing N/P dopants in PMOS and NMOS fins at the SSRW layer without complicated processing and the resulting device are provided. Embodiments...
US-9,455,203 Low threshold voltage CMOS device
A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a...
US-9,455,202 Mask set and method for fabricating semiconductor device by using the same
A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a...
US-9,455,201 Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits
In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect...
US-9,455,200 Method for semiconductor device fabrication
A method of forming a semiconductor device includes receiving a substrate with a gate structure and forming a spacer layer over the substrate and the gate...
US-9,455,199 Methods of forming strained and relaxed germanium fins for PMOS and NMOS finFET devices, respectively
One illustrative method disclosed herein includes, among other things, forming a first fin for the PMOS device and a second fin for the NMOS device, wherein...
US-9,455,198 Methods of removing fins so as to form isolation structures on products that include FinFET semiconductor devices
One illustrative method disclosed herein includes, among other things, removing at least one, but not all, of a plurality of first features in a first patterned...
US-9,455,197 Method for manufacturing silicon carbide semiconductor device
When a gate insulating film is formed on a silicon carbide substrate, the silicon carbide substrate is first oxidized with an oxidation reactant gas to form the...
US-9,455,196 Method for improving fin isolation
A method of processing a workpiece to create a doped fin structure is disclosed. A portion of the workpiece is subjected to a pre-amorphizing implant to create...
US-9,455,195 Method of forming performance optimized gate structures by silicidizing lowered source and drain regions
A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type...
US-9,455,194 Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region...
US-9,455,193 Integrated circuit interposer and method of manufacturing the same
Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is...
US-9,455,192 Kerf preparation for backside metallization
In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes attaching a substrate to a carrier using an...
US-9,455,191 Shielded coplanar line
In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line,...
US-9,455,190 Semiconductor apparatus having TSV and testing method thereof
A test method of a semiconductor apparatus before a wafer is ground may include applying voltages to a bump electrically coupled to a through-silicon via (TSV)...
US-9,455,189 Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and...
A plurality of semiconductor memory devices on a multi-chip package is disclosed. Each semiconductor device may include a plurality of through vias and a...
US-9,455,188 Through silicon via device having low stress, thin film gaps and methods for forming the same
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a "buffer zone" or gap layer...
US-9,455,187 Backside device contact
Methods for fabricating a backside device contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle...
US-9,455,186 Selective local metal cap layer formation for improved electromigration behavior
A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD);...
US-9,455,185 Laser anneal of buried metallic interconnects including through silicon vias
Disclosed is a process of annealing through silicon vias (TSVs) or other deeply buried metallic interconnects using a back side laser annealing process. The...
US-9,455,184 Aluminum interconnection apparatus
A method comprises depositing a first alloy layer over a substrate, depositing a metal layer over the first alloy layer, depositing a second alloy layer over...
US-9,455,183 Semiconductor device and bump formation process
A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the...
US-9,455,182 Interconnect structure with capping layer and barrier layer
Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect...
US-9,455,181 Vias in porous substrates
A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of...
US-9,455,180 Controlled spalling of fine features
In one example, a method for fabricating a device includes patterning a substrate with a set of features forming a portion of the device, depositing a first...
US-9,455,179 Methods to reduce debonding forces on flexible semiconductor films disposed on vapor-releasing adhesives
A method comprises providing a handle substrate having a front surface and a back surface; providing a layer of flexible semiconductor material having a front...
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