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Patent # Description
US-9,461,168 Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices
A multi-gate finFET structure and formation thereof. The multi-gate finFET structure has a first gate structure that includes an inner side and an outer side....
US-9,461,167 Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating...
An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
US-9,461,166 Lateral-diffused metal oxide semiconductor device and fabricating method thereof
A lateral-diffused metal oxide semiconductor device including a substrate, a second deep well, a gate, a source, a drain and a first dopant region is provided....
US-9,461,165 Semiconductor device with an SGT and method for manufacturing the same
A semiconductor device includes a P.sup.+ region and an N.sup.+ region functioning as sources of SGTs and disposed in top portions of Si pillars formed on an...
US-9,461,164 Semiconductor device and method of manufacturing the same
A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further...
US-9,461,163 Semiconductor device including Schottky barrier diode and power MOSFETs and a manufacturing method of the same
In a non-insulated DC-DC converter having a circuit in which a power MOS.cndot.FET high-side switch and a power MOS.cndot.FET low-side switch are connected in...
US-9,461,162 Semiconductor integrated circuit device having reduced unit cell area
A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor...
US-9,461,161 Memory element circuitry with minimum oxide definition width
Integrated circuits with memory circuitry are provided. The memory circuitry may include memory cell transistors and associated pass transistors. The memory...
US-9,461,160 Non-planar III-N transistor
Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and...
US-9,461,159 Self-stop gate recess etching process for semiconductor field effect transistors
A field effect transistor (FET) device including a GaAs substrate, an AlGaAs buffer layer provided on the substrate, an InGaAs channel layer provided on the...
US-9,461,158 Heterojunction field effect transistor
A heterojunction field effect transistor includes a first contact portion and a second contact portion. A length of the first contact portion in a longitudinal...
US-9,461,157 Nanowire electric field effect sensor having three-dimensional stacking structure nanowire and manufacturing...
The present invention provides a nanowire sensor comprising nanowires, in which the nanowires are stacked to form a three-dimensional structure so that they...
US-9,461,156 Memory structrue and operation method thereof
This invention provides a memory structure and an operation method thereof. The memory structure includes a triode for alternating current (TRIAC) and a memory...
US-9,461,155 Thyristor random access memory device and method
Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased...
US-9,461,154 Trench gate MOS semiconductor device and method for manufacturing the same
A p-type base region, in which an n.sup.+ emitter region is formed, and a p-type floating region are provided in a surface layer of one main surface of an...
US-9,461,153 Devices and methods related to a barrier for metallization of a gallium based semiconductor
Disclosed are structures and methods related to a barrier layer for metallization of a selected semiconductor such as indium gallium phosphide (InGaP). In some...
US-9,461,152 Semiconductor device
A semiconductor device includes a first main electrode; a second main electrode; a first semiconductor region of a first conductivity type; a second...
US-9,461,151 Dual storage node memory
An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage...
US-9,461,150 Method for fabricating semiconductor device with fin-shaped structure
A method for fabricating semiconductor device with fin-shaped structure is disclosed. The method includes the steps of: forming a fin-shaped structure on a...
US-9,461,149 Nanowire structure with selected stack removed for reduced gate resistance and method of fabricating same
Methods to fabricate a stacked nanowire field effect transistor (FET) with reduced gate resistance are provided. The nanowire stack in the stacked nanowire FET...
US-9,461,148 Semiconductor device and method of fabricating the same
A method of fabricating a semiconductor device is described. The method of fabricating a semiconductor device comprises providing a fin formed to protrude from...
US-9,461,147 Semiconductor structure
The present invention provides a semiconductor structure, including a substrate, having a fin structure disposed thereon, a gate structure, crossing over parts...
US-9,461,146 Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy
A method of making a semiconductor device includes forming a gate covered by a hard mask over a substrate; disposing a mask over the gate and the hard mask;...
US-9,461,145 OPC enlarged dummy electrode to eliminate ski slope at eSiGe
Enlarging the dummy electrode to the STI top width size by OPC cut mask correction and the resulting device are disclosed. Embodiments include forming an STI...
US-9,461,144 Method for semiconductor device fabrication
A method of forming a semiconductor device is disclosed. The method includes exposing a dummy oxide layer of a gate structure to a vapor mixture comprising...
US-9,461,143 Gate contact structure over active gate and method to fabricate same
Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor...
US-9,461,142 Fabrication method of an improved field effect device
A SOI substrate is covered by a semiconductor material pattern which comprises a dividing pattern made from electrically insulating material. The dividing...
US-9,461,141 Contact techniques and configurations for reducing parasitic resistance in nanowire transistors
Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one...
US-9,461,140 Semiconductor device manufacturing method including a counter layer for power conversion
A p-type base layer is selectively formed on a surface of an n-type drift layer; an n-type source layer is selectively formed on a surface of the p-type base...
US-9,461,139 Lateral bipolar junction transistor (BJT) on a silicon-on-insulator (SOI) substrate
A bipolar transistor is supported by a substrate including a semiconductor layer overlying an insulating layer. A transistor base is formed by a base region in...
US-9,461,138 Non-volatile semiconductor memory with nitride sidewall contacting nitride layer of ONO gate stack and methods...
A non-volatile semiconductor memory free from adverse effects due to process charge is provided. The non-volatile semiconductor memory includes: a silicon...
US-9,461,137 Tungsten silicide nitride films and methods of formation
Embodiments of the present disclosure include tungsten silicide nitride films and methods for depositing tungsten silicide nitride films. In some embodiments, a...
US-9,461,136 Memory device and method of fabricating thereof
Subject matter disclosed herein relates to a process flow to form a gate structure of a memory device.
US-9,461,135 Nitride semiconductor device with multi-layer structure electrode having different work functions
A semiconductor device includes first, a second, and third semiconductor layers respectively made of a nitride semiconductor and stacked on a substrate, a drain...
US-9,461,134 Method for forming source/drain contact structure with chalcogen passivation
In some embodiments, an MIS-type contact structure is formed by passivating the semiconductor surface of a source/drain region with a chalcogen, and...
US-9,461,133 High voltage metal-oxide-semiconductor transistor device having stepped gate structure and manufacturing method...
A high voltage metal-oxide-semiconductor transistor device having stepped gate structure and a manufacturing method thereof are provided. The manufacturing...
US-9,461,132 Semiconductor device having mid-gap work function metal gate electrode
Provided is a semiconductor device having mid-gap work function metal gate electrodes. The semiconductor device includes a plurality of gate patterns, and the...
US-9,461,131 High quality deep trench oxide
An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio...
US-9,461,130 Electronic device comprising conductive regions and dummy regions
A device includes an epitaxial region extending into a front surface of a chip. A portion of the chip adjacent the epitaxial region defines a collector. A gate...
US-9,461,129 Memory cell having a vertical selection gate formed in an FDSOI substrate
A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the...
US-9,461,128 Method for creating self-aligned transistor contacts
Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is...
US-9,461,127 Vertical power MOSFET having planar channel and its method of fabrication
A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. An...
US-9,461,126 Transistor, clocked inverter circuit, sequential circuit, and semiconductor device including sequential circuit
A transistor with excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) is provided. The transistor...
US-9,461,125 Method of preparing monoatomic layer black phosphorous by irradiating ultrasound
A method of preparing monoatomic layer black phosphorous by irradiating an ultrasound includes: putting black phosphorus into a solvent and irradiating the...
US-9,461,124 Ga.sub.2O.sub.3 semiconductor element
A Ga.sub.2O.sub.3 semiconductor element, includes: an n-type .beta.-Ga.sub.2O.sub.3 substrate; a .beta.-Ga.sub.2O.sub.3 single crystal film, which is formed on...
US-9,461,123 Semiconducting component
This invention relates to an electronic semiconductive component comprising at least one layer (2,3) of a p-type or n-type material, wherein the layer of a said...
US-9,461,122 Semiconductor device and manufacturing method for the same
A semiconductor device includes: a first GaN based semiconductor layer (hereinafter abbreviated as GaN layer); a second GaN layer on the first GaN layer and...
US-9,461,121 Process for the manufacture of a doped III-N bulk crystal and a free-standing III-N substrate, and doped III-N...
A process for producing a doped III-N bulk crystal, wherein III denotes at least one element of the main group III of the periodic system, selected from Al, Ga...
US-9,461,120 Electronic device
According to various embodiments, an electronic device may include: a layer including a two-dimensional material; a dielectric structure at a first side of the...
US-9,461,119 Semiconductor structure with compositionally-graded transition layer
The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor...
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