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Patent # Description
US-9,461,017 Electronic package that includes a plurality of integrated circuit devices bonded in a three-dimensional stack...
An electronic package comprising a plurality of vertically stacked integrated circuit (IC) devices including a first IC device and a second IC device is...
US-9,461,016 Semiconductor device
To improve reliability of signal transmission of an interposer which couples between semiconductor chips. A reference potential wiring and a reference potential...
US-9,461,015 Enhanced stacked microelectronic assemblies with central contacts
A microelectronic assembly includes a dielectric element having first and second surfaces, first and second apertures extending between the first and second...
US-9,461,014 Methods of forming ultra thin package structures including low temperature solder and structures formed therby
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include...
US-9,461,013 Wire spool system for a wire bonding apparatus
Disclosed is a wire spool system for a wire bonding apparatus, comprising: a wire reel arranged to receive a wire; a wire guide for feeding a free end of the...
US-9,461,012 Copper ball bond features and structure
An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash...
US-9,461,011 Method and apparatus for manufacturing lead frames
An embodiment of a method and an apparatus for manufacturing lead frames are described. For example, a coating layer is formed on one or more predefined...
US-9,461,010 Debond interconnect structures
The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to...
US-9,461,009 Method and apparatus for assembling a semiconductor package
A method of packaging a semiconductor device is described. The method includes: attaching a first surface of a semiconductor die to a carrier; forming one or...
US-9,461,008 Solder on trace technology for interconnect attachment
A solder on trace device includes a conductive trace on a semiconductor substrate surface. The conductive trace has a sidewall and a bonding surface. The solder...
US-9,461,007 Wafer-to-wafer bonding structure
A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that...
US-9,461,006 Integrated circuit protection layer used in a capacitive capacity
In one exemplary embodiment of the invention, an apparatus includes: at least one functional circuit; and an electrically-conductive protective layer on a...
US-9,461,005 RF package with non-gaseous dielectric material
An RF package including: an RF circuit; a non-gaseous dielectric material coupled to the RF circuit, and having a thickness based on a magnetic field in the RF...
US-9,461,004 Semiconductor workpiece having a semiconductor substrate with at least two chip areas
A semiconductor workpiece includes a semiconductor substrate, at least two chip areas, components of semiconductor devices being formed in the semiconductor...
US-9,461,003 Semiconductor devices having shielding pattern
A semiconductor device includes a circuit pattern on a substrate, a shielding pattern on the circuit pattern and constituted by a plurality of parallel bars,...
US-9,461,002 Semiconductor device
A semiconductor device and a method of making the same. The semiconductor device includes a semiconductor substrate mounted on a carrier. The semiconductor...
US-9,461,001 Semiconductor device package integrated with coil for wireless charging and electromagnetic interference...
The present disclosure relates to a semiconductor device package which includes a carrier, an electronic component, conductive elements, a package body, a...
US-9,461,000 Parallel signal via structure
A silicon interposer with redundant thru-silicon vias. The silicon interposer includes a first trace structure on a first side of the interposer and a second...
US-9,460,999 Solution process for improved nanowire electrodes and devices that use the electrodes
A method of producing an electro-optic device includes providing a substructure, depositing a network of nanowires on the substructure, depositing a sol-gel...
US-9,460,998 Semiconductor constructions and methods of forming semiconductor constructions
Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between...
US-9,460,997 Interconnect structure for semiconductor devices
An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a...
US-9,460,996 Integrated device with inductive and capacitive portions and fabrication methods
Integrated devices and fabrication methods thereof are presented. The methods include, for instance fabricating an integrated device comprising an inductive...
US-9,460,995 Semiconductor device and structure therefor
In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of...
US-9,460,993 Interposer with signal-conditioned edge probe points
An interposer comprising an array of top contacts on the top surface configured to interface with an integrated circuit package, a corresponding array of bottom...
US-9,460,992 Packaging substrate having a through-holed interposer
A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on...
US-9,460,991 Semiconductor device and structure
A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second...
US-9,460,990 Substrates and semiconductor packages including the same, electronic systems including the semiconductor...
A substrate may include a body having a first surface and a second surface opposite to each other, at least one first wiring pattern disposed on the first...
US-9,460,989 Interposer having a defined through via pattern
A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the...
US-9,460,988 Interconnect structures
A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The...
US-9,460,987 Interconnect structure for package-on-package devices and a method of fabricating
An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon...
US-9,460,986 Method of manufacturing semiconductor package substrate with limited use of film resist and semiconductor...
A method of manufacturing a semiconductor package substrate has a simplified process and an upper and lower pattern alignment problem is solved. A semiconductor...
US-9,460,985 Cooling apparatuses having a jet orifice surface with alternating vapor guide channels
Jet-impingement, two-phase cooling apparatuses having alternating vapor outlet channels are disclosed. In one embodiment, a cooling apparatus includes a fluid...
US-9,460,984 Heat dissipating circuit board and electronic device
A heat dissipating circuit board for a power semiconductor includes an electrode material on which a power semiconductor is mounted on a front surface thereof,...
US-9,460,983 Joining structure using thermal interface material
A thermal interface material includes a metal foil, which has a first surface and an opposite second surface, and a plurality of rod conductors each having a...
US-9,460,982 Integrated heat spreader for multi-chip packages
An integrated heat spreader comprising a heat spreader frame that has a plurality of openings formed therethrough and a plurality of thermally conductive...
US-9,460,981 Semiconductor module
A semiconductor module uses pin bonding and improves cooling capacity. The semiconductor module includes a semiconductor element; a pin electrically and...
US-9,460,980 Systems, apparatus, and methods for heat dissipation
Some examples of the disclosure include a semiconductor package having a heat spreader, an outer perimeter portion attached to the bottom of the heat spreader...
US-9,460,979 Electronic device having heat conducting member
An electronic device includes a semiconductor module, a wiring substrate, a case member and a heat conducting member. The heat conducting member thermally...
US-9,460,978 Semiconductor device and structure
A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second...
US-9,460,977 Package-on-Package with via on pad connections
An interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, and a metal pad underlying the conductive...
US-9,460,976 Encapsulated arrays of electronic switching devices
An electronic switching device array encapsulated in an encapsulating structure; wherein said array is exposed to one or more gas pockets between said array and...
US-9,460,975 DFT structure for TSVs in 3D ICs while maintaining functional purpose
Methods of testing TSVs using eFuse cells prior to and post bonding wafers in a 3D IC stack are provided. Embodiments include providing a wafer of a 3D IC...
US-9,460,974 Oxide formation in a plasma process
A method of making a semiconductor structure is provided. The method includes forming a tunneling layer overlying a first channel connecting a source and a...
US-9,460,973 Surface processing progress monitoring system
A system including an index assigning section estimating the thickness of a thin film based on the intensity of light reflected on a substrate and a theoretical...
US-9,460,972 Semiconductor device and method of forming reduced surface roughness in molded underfill for improved C-SAM...
A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is...
US-9,460,971 Method to co-integrate oppositely strained semiconductor devices on a same substrate
Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained,...
US-9,460,970 Control fin heights in FinFET structures
A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin...
US-9,460,969 Macro to monitor n-p bump
A technique relates to fabricating a macro for measurements utilized in dual spacer, dual epitaxial transistor devices. The macro is fabricated according to a...
US-9,460,968 Fin shape for fin field-effect transistors and method of forming
A fin field-effect transistor (finFET) and a method of forming are provided. A gate electrode is formed over one or more fins. Notches are formed in the ends of...
US-9,460,967 Method of manufacturing semiconductor chip, semiconductor chip, and semiconductor device
A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each...
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