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Patent # Description
US-9,460,966 Method and apparatus for dicing wafers having thick passivation polymer layer
Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of...
US-9,460,965 Semiconductor substrate, eletronic device and method for manufacturing the same
A semiconductor substrate includes a vertical conductor and an insulating layer. The vertical conductor includes a metal/alloy component of a nanocomposite...
US-9,460,964 Method for forming void-free polysilicon and method for fabricating semiconductor device using the same
A method for fabricating a semiconductor device includes forming a buried gate electrode in a semiconductor substrate. An insulating layer is formed over the...
US-9,460,963 Self-aligned contacts and methods of fabrication
Embodiments of the present invention provide an improved contact and method of fabrication. A dielectric layer is formed over transistor structures which...
US-9,460,962 Substrate contact etch process
A semiconductor device with a deep trench has a dielectric liner formed on sidewalls and a bottom of the deep trench. A pre-etch deposition step of a two-step...
US-9,460,961 Techniques and apparatus for anisotropic metal etching
In one embodiment, a method for etching a copper layer disposed on a substrate includes directing reactive ions to the substrate when a mask that defines an...
US-9,460,960 Electric connection element manufacturing method
A surface of a silicon substrate is coated with a silicon oxide layer. A manganese silicate layer is then deposited on the silicon oxide layer using a process...
US-9,460,959 Methods for pre-cleaning conductive interconnect structures
Methods for processing a substrate are provided herein. In some embodiments, method of processing a substrate includes: heating a substrate disposed within a...
US-9,460,958 Air gap isolation in non-volatile memory
Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a...
US-9,460,957 Method and structure for nitrogen-doped shallow-trench isolation dielectric
An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method...
US-9,460,956 Method of forming shallow trench isolation and semiconductor device
According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; a first vertical structure protruding...
US-9,460,955 Integrated circuits with shallow trench isolations, and methods for producing the same
Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method...
US-9,460,954 Method of clamping a substrate and clamp preparation unit using capillary clamping force
The invention relates to a method of clamping a substrate on a surface of a substrate support structure. First, a liquid is applied on a surface of the...
US-9,460,953 Edge grip substrate handler
A mechanism for handling substrates such as semiconductor wafers is disclosed. The mechanism supports the substrate in a tilted orientation to ensure that...
US-9,460,952 Film for pressure-sensitive adhesive tape and pressure-sensitive adhesive tape
A film for a pressure-sensitive adhesive tape is a film for a pressure-sensitive adhesive tape, including a non-pressure-sensitive adhesive layer on one surface...
US-9,460,951 Semiconductor device and method of wafer level package integration
A method of making a wafer level chip scale package includes providing a temporary substrate, and forming a wafer level interconnect structure over the...
US-9,460,950 Wafer carrier for smaller wafers and wafer pieces
Embodiments described herein relate to an apparatus and method for securing and transferring substrates. A substrate carrier, having one or more electrostatic...
US-9,460,949 Ultra-low oxygen and humility loadport and stocker system
One or more apparatuses for adjusting at least one of an oxygen content or a water content in a pod and methods of their use are provided, where one or more...
US-9,460,948 Data management
A package is provided for use with a track-and-trace data management system. The package comprises a base defining a plurality of compartments, each compartment...
US-9,460,947 Coating and developing apparatus and method, and storage medium
In one embodiment, a coating and developing apparatus is provided with transfer units, provided between a stack of early-stage processing unit blocks and a...
US-9,460,946 Substrate processing apparatus and heating equipment
A substrate processing apparatus includes a heating part including a cylindrical-shaped heat insulator and a heating wire arranged on the inner circumferential...
US-9,460,945 Substrate processing apparatus for semiconductor devices
A substrate processing apparatus comprises a processing chamber for processing a substrate, a substrate supporting tool for supporting and carrying the...
US-9,460,944 Substrate treating apparatus and method of treating substrate
A substrate treating apparatus includes a rotating and holding unit that rotates a substrate, a first supply source that supplies first pure water having a...
US-9,460,943 Gas-liquid two-phase atomizing cleaning device and cleaning method
The present invention provides a gas-liquid two-phase atomizing cleaning device. The cleaning device comprises a gas-liquid two-phase atomizing spray head. The...
US-9,460,942 Substrate treatment system, substrate transfer method and computer storage medium
An interface station of a coating and developing treatment system has: a cleaning unit cleaning at least a rear surface of a wafer before the wafer is...
US-9,460,941 Substrate cleaning apparatus and substrate processing apparatus including the substrate cleaning apparatus
An ULPA filter is arranged at the upper portion in a casing. Air outside of the casing is supplied to the ULPA filter through a duct. Clean air that has passed...
US-9,460,940 Method for manufacturing semiconductor device and manufacturing apparatus of semiconductor device
A semiconductor device including an oxide semiconductor and an organic resin film is manufactured in the following manner. Heat treatment is performed on a...
US-9,460,939 Package-on-package structures and methods of manufacture thereof
A method for manufacturing a package-on-package structure may include: providing a support structure having a package attached to an inclined surface of the...
US-9,460,938 Semiconductor device including a plurality of semiconductor chips, and a cover member with first and second brims
The long sides of a rectangular control chip and the long sides of a rectangular memory chip are arranged parallel with first sides of the upper surface of a...
US-9,460,937 Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages
Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may...
US-9,460,936 Semiconductor device and method of manufacturing the same
The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the...
US-9,460,935 Method for fabricating semiconductor devices
The invention relates to a method for fabricating a semiconductor device. The method comprises forming a first etching layer and a second etching layer stacked...
US-9,460,934 Wet strip process for an antireflective coating layer
An silicon-containing antireflective coating (SiARC) material is applied on a substrate. The SiARC material which includes a base polymer and may include a...
US-9,460,933 Patterning method
A patterning method is provided. Mask structures including first mask layers and first photoresist layers are formed sequentially on a material layer. A second...
US-9,460,932 Surface poisoning using ALD for high selectivity deposition of high aspect ratio features
Methods of selectively depositing a feature onto a substrate surface while maintaining substantially straight sidewalls on the feature. A portion of the feature...
US-9,460,931 High aspect ratio memory hole channel contact formation
A memory device and a method of fabricating a memory device that includes forming a protrusion over a substrate, an etch stop layer over the protrusion, and a...
US-9,460,930 Method for performing laser crystallization
A method for performing a laser crystallization is provided. The method includes generating a laser beam, refracting the laser beam to uniformize an intensity...
US-9,460,929 Method of manufacturing semiconductor device
Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating...
US-9,460,928 Method for manufacturing semiconductor devices
A semiconductor device manufacturing method includes preparing a wafer having projections formed on a substrate. The projections project upward from a surface...
US-9,460,927 Semiconductor device manufacturing method
A semiconductor device manufacturing method for a semiconductor device having a p-n junction formed of a first conductivity type first semiconductor region and...
US-9,460,926 Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions
A power integrated circuit includes a junction field effect transistor (JFET) device formed in a first portion of a semiconductor layer with a gate region being...
US-9,460,925 System and apparatus for efficient deposition of transparent conductive oxide
A substrate processing system that includes a substrate processing chamber having one or more sidewalls that at least partially define a substrate processing...
US-9,460,924 Semiconductor device having structure with fractional dimension of the minimum dimension of a lithography system
A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the...
US-9,460,923 Method of forming a strained silicon layer
The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate;...
US-9,460,922 Laser annealing apparatus and a method for manufacturing a display apparatus using the laser annealing apparatus
A method of manufacturing a display apparatus includes forming an amorphous silicon layer on a substrate, splitting a first laser beam emitted from a first...
US-9,460,921 Nanowire article and processes for making and using same
A nanowire article includes a substrate; a plurality of nanowires disposed on the substrate, the nanowires comprising a semiconductor nitride, the semiconductor...
US-9,460,920 Horizontal gate all around device isolation
Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising...
US-9,460,919 Manufacturing method of two-dimensional transition-metal chalcogenide thin film
A manufacturing method of a two-dimensional transition-metal chalcogenide thin film includes providing a substrate, providing a reaction film, providing a...
US-9,460,918 Epitaxy of high tensile silicon alloy for tensile strain applications
Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a...
US-9,460,917 Method of growing III-N semiconductor layer on Si substrate
A method of growing III-N semiconducting material on a silicon substrate including the steps of growing a layer of epitaxial rare earth oxide on a single...
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