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Memory tester design for soft error rate (SER) failure analysis
A method of determining multi-bit upsets (MBU) during soft error rate (SER) testing of a memory device under test is provided. The method may include receiving...
According to one embodiment, there is provided a memory system that is connected to a host apparatus. The memory system includes a transmitting port and a...
Semiconductor devices and semiconductor systems including the same
A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a first test start signal...
Read only memory (ROM) with redundancy
A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit...
Method and device for evaluating a chip manufacturing process
A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing...
AC stress mode to screen out word line to word line shorts
A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of...
Method and device for controlling a sample and hold circuit
A method is provided for controlling a sample and hold circuit that includes a switching module coupled to a storage capacitor. A circuit external to the sample...
One-time programmable memory devices using FinFET technology
An OTP (One-Time Programmable) element can be fabricated in CMOS FinFET processes are disclosed. The OTP cell can be implemented as a MOS device, dummy-gate...
Method for creating an OTPROM array possessing multi-bit capacity with
TDDB stress reliability mechanism
A method of forming an OTPROM capable of storing twice the number of bits as a conventional OTPROM without increasing the overall size of the device is...
Word line dependent channel pre-charge for memory
Techniques are provided for programming a memory device. A pre-charge phase is used to boost the channel of an unselected NAND string by allowing a bit line...
Semiconductor memory device for storing multivalued data
Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first...
Data path with clock-data tracking
A system includes a plurality of sensing devices, a first multiplexer, a plurality of local return clock signal paths, a second multiplexer, and a data latch....
Maintaining versions of data in solid state memory
Various embodiments are directed to maintaining versions of data within a solid state memory. At least one request to write at least one dataset to a logical...
Method and system for determining storing state of flash memory
A method for determining a storing state of a flash memory is provided. The method includes the following steps. Firstly, plural first specific cell patterns...
Nonvolatile memory system and refresh method
A memory system including non-volatile memory devices and a corresponding refresh method are disclosed. The method groups memory blocks of the non-volatile...
Recovery of partially programmed block in non-volatile memory
Techniques for recovery of partially programmed blocks in non-volatile storage are disclosed. After programming memory cells in an open region of a partially...
Page or word-erasable composite non-volatile memory
A non-volatile memory includes bit lines, a first page-erasable sector including memory cells of a first type, and a second word-erasable or bit-erasable sector...
Non-volatile memory cell structure and non-volatile memory apparatus using
The invention provides a non-volatile memory cell structure and non-volatile memory apparatus using the same. The non-volatile memory cell structure includes a...
Memory system, program method thereof, and computing system including the
Disclosed is a memory system and a method of programming a multi-bit flash memory device which includes memory cells configured to store multi-bit data, where...
Nonvolatile memory device, a storage device having the same and an
operating method of the same
An operating method of a nonvolatile memory device including a plurality of strings each string including at least two pillars penetrating wordlines disposed at...
Nonvolatile semiconductor memory device
In a writing operation, a control circuit raises the voltage of a writing-prohibited bit line among a plurality of bit lines to a first voltage, and thereafter...
Semiconductor memory device
A semiconductor memory device may include: a memory cell array having a plurality of memory cells, a plurality of word lines and a plurality of bit lines; a...
Apparatuses and methods for segmented SGS lines
Apparatuses and methods for segmented SGS lines are described. An example apparatus may include first and second pluralities of memory subblocks of a memory...
Data clock synchronization in hybrid memory modules
Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a...
Semiconductor memory having both volatile and non-volatile functionality
and method of operating
Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells...
Non-volatile digital memory including thin film resistors
A non-volatile digital memory includes: a plurality of thin film resistors; and a control circuit adapted to: program, during a first programming phase, the...
Non-volatile memory cell utilizing volatile switching two terminal device
and a MOS transistor
A non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive...
Semiconductor integrated circuit device including a leakage current
sensing unit and method of operating the same
A semiconductor integrated circuit device configured for sensing a pure leakage current of a cell array and improving a read error is disclosed. The...
Semiconductor storage device
A semiconductor storage device according to the present embodiment includes a constant current source. A reference current path is connected to the constant...
Reference voltage generation apparatuses and methods
A method and apparatuses for generating a reference voltage are disclosed. One example apparatus includes a current source coupled to a first power supply. The...
Determining soft data
The present application includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data...
Method of operating memory controller and devices including memory
A method of operating a memory controller includes receiving a first data sequence and generating a coset representative sequence that can be divided into m-bit...
Memory system and memory control method
According to one embodiment, a memory system includes a non-volatile memory, a memory interface, an encoder configured to generate eight code words, and a...
Initialization techniques for multi-level memory cells using multi-pass
Methods are provided for programming multi-level non-volatile memory cells, the multi-level non-volatile memory cells accessible by a plurality of word lines....
Memory sensing method using one-time sensing table and associated memory
A memory sensing method is provided. The memory sensing method comprises the following steps: sensing a first memory unit to obtain a first sensing result;...
Static random access memory with bitline boost
A static random access memory includes a memory cell array, a control logic configured to generate a first write clock signal and a second write clock signal...
SRAM read buffer with reduced sensing delay and improved sensing margin
A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a...
SRAM voltage assist
The disclosure provides for an SRAM array having a plurality of wordlines and a plurality of bitlines, referred to generally as SRAM lines. The array has a...
Sense amplifier driving device and semiconductor device including the same
A sense amplifier driving device may include a sense amplifier driving block configured to supply a post overdriving voltage to a pull-up power line coupled to...
Self-refresh device and semiconductor device including the self-refresh
A self-refresh device is disclosed, which relates to a technology for generating a self-refresh period by reflecting refresh characteristics of an actual cell...
Fast exit from DRAM self-refresh
Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low...
Provided is a memory device in which memory capacity per unit area is increased without making the manufacturing process complicated. The memory device includes...
Two-transistor thyristor SRAM circuit and methods of operation
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select...
Methods of operating ferroelectric memory cells, and related ferroelectric
Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric...
Electric field ferromagnetic resonance excitation method and magnetic
function element employing same
To realize an electric field-driven type ferromagnetic resonance excitation method of low power consumption using an electric field as drive power, and provide...
Cross point array MRAM having spin hall MTJ devices
Cross point array magnetoresistive random access memory (MRAM) implementing spin hall magnetic tunnel junction (MTJ)-based devices and methods of operation of...
Semiconductor memory device
A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit...
Memory device, and memory system including the same
A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to...
Semiconductor apparatus having control block generating column select
signal and overdrive signal
A semiconductor apparatus includes a control block configured to control a pulse width of a column select signal in response to a precharge command from an...
Buffer control circuit of semiconductor memory apparatus
A buffer control circuit of a semiconductor memory apparatus includes a delay unit configured to determine delay amounts for a command in response to a...