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Patent # Description
US-9,466,717 Complex semiconductor devices of the SOI type
The present disclosure provides, in a first aspect, a semiconductor device including an SOI substrate portion, a gate structure formed on the SOI substrate...
US-9,466,716 Dual-SiGe epitaxy for MOS devices
A semiconductor includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor having at least a portion in the semiconductor...
US-9,466,715 MOS transistor having a gate dielectric with multiple thicknesses
A novel MOS transistor including a well region, a gate dielectric layer, a gate electrode, a source region and a drain region is provided. The well region of a...
US-9,466,714 Vertical tunneling field-effect transistor cell with coaxially arranged gate contacts and drain contacts
A tunneling field-effect transistor (TFET) device includes a source region, a gate stack, and a drain region. The TFET device further includes a source contact...
US-9,466,713 Non-floating vertical transistor structure
A non-floating vertical transistor includes a substrate and a protuberant structure extending from the substrate. A segregating pillar is inside the protuberant...
US-9,466,712 Resurf semiconductor device charge balancing
Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift...
US-9,466,711 Semiconductor device
Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current...
US-9,466,710 Source and body contact structure for trench-DMOS devices using polysilicon
A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate...
US-9,466,709 Silicon-carbide trench gate MOSFETs
In a general aspect, an apparatus can include a semiconductor substrate, a drift region disposed in the semiconductor substrate; a body region disposed in the...
US-9,466,708 Method of forming a transistor and structure therefor
In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of...
US-9,466,707 Planar mosfets and methods of fabrication, charge retention
A planar MOSFET includes a plurality of MOSFET cells. Each MOSFET cell includes an epitaxial layer of a first conductivity type, a body region of a second...
US-9,466,706 Semiconductor device including first and second gate insulating films disposed on a semiconductor layer and...
A semiconductor device, comprises: a semiconductor layer, a first gate insulating film, a second gate insulating film and a gate electrode. The semiconductor...
US-9,466,705 Semiconductor device and method of manufacturing the same
A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the...
US-9,466,704 Nonvolatile memory device and method of manufacturing the same
A nonvolatile memory device and method of manufacturing the same are provided. In the nonvolatile memory device, a blocking insulation layer is provided between...
US-9,466,703 Method for fabricating semiconductor device
Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second...
US-9,466,702 Semiconductor device including multiple fin heights
A semiconductor device comprising a substrate, an base layer disposed on the substrate having a thickness C in first area and a thickness B in a second area and...
US-9,466,701 Processes for preparing integrated circuits with improved source/drain contact structures and integrated...
Processes for preparing an integrated circuit for contact landing, processes for fabricating an integrated circuit, and integrated circuits prepared according...
US-9,466,700 Semiconductor device and method of fabricating same
A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first...
US-9,466,699 Manufacturing method for vertical channel gate-all-around MOSFET by epitaxy processes
A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first epitaxial...
US-9,466,698 Electronic device including vertical conductive regions and a process of forming the same
An electronic device can include different vertical conductive structures that can be formed at different times. The vertical conductive structures can have the...
US-9,466,697 Semiconductor devices and methods of manufacturing the same
Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of...
US-9,466,696 FinFETs and methods for forming the same
A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation...
US-9,466,695 Valve for fluid circulation
A valve is provided with a casing forming an enclosure for fluid flow with a fluid inlet and outlet, a shutter cooperating with a seat integral with the casing...
US-9,466,694 Metal-oxide-semiconductor transistor device and manufacturing method thereof
A method for manufacturing a MOS transistor device includes following steps. A substrate including at least an isolation structure formed therein is provided....
US-9,466,693 Self aligned replacement metal source/drain finFET
A method of a fin-shaped field effect transistor (finFET) device includes forming at least one fin that extends in a first direction; covering the fin with a...
US-9,466,692 Method to improve reliability of replacement gate device
A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k...
US-9,466,691 Fin shaped structure and method of forming the same
A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed...
US-9,466,690 Precisely controlling III-V height
After forming trenches extending through a dielectric material stack including, from bottom to top, a first dielectric layer, a second dielectric layer and a...
US-9,466,689 Method for manufacturing a semiconductor device and semiconductor device manufactured thereby
A semiconductor device includes an input electrode provided on a front surface of a semiconductor substrate of a first conductivity type and an output electrode...
US-9,466,688 Semiconductor device with multilayer contact and method of manufacturing the same
The present invention provides a semiconductor with a multilayered contact structure. The multilayered structure includes a metal contact placed on an active...
US-9,466,687 Methods for producing bipolar transistors with improved stability
Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base...
US-9,466,686 Graphene devices with local dual gates
An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with...
US-9,466,685 Semiconductor structure including at least one electrically conductive pillar, semiconductor structure...
A semiconductor structure includes a substrate, at least one electrically conductive pillar provided over the substrate and an electrically conductive structure...
US-9,466,684 Transistor with diamond gate
A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN ...
US-9,466,683 Semiconductor device
A semiconductor device includes a pillar-shaped silicon layer on a fin-shaped silicon layer. A gate insulating film and a metal gate electrode are around the...
US-9,466,682 Thin film transistor array panel
A thin film transistor array panel is capable of increasing an aperture ratio and decreasing parasitic capacitance between a gate electrode and a drain...
US-9,466,681 Method and apparatus for forming a semiconductor gate
The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a...
US-9,466,680 Integrated multiple gate length semiconductor device including self-aligned contacts
A multi-channel semiconductor device includes a first and second gate channels formed in a semiconductor substrate. The first gate channel has a first length...
US-9,466,679 All around contact device and method of making the same
A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region...
US-9,466,678 Semiconductor device and manufacturing method thereof
The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, an epitaxial...
US-9,466,677 Semiconductor structure including guard ring
One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer...
US-9,466,676 Method for forming a semiconductor device having a metal gate recess
Provided are approaches of forming a semiconductor device (e.g., transistor such as a FinFET or planar device) having a gate metal recess. In one approach, a...
US-9,466,675 Method of manufacturing silicon carbide semiconductor device
A recess is formed by partially etching a silicon carbide substrate. A mask layer is formed on the silicon carbide substrate by means of photolithography using...
US-9,466,674 Semiconductor devices with non-implanted barrier regions and methods of fabricating same
An electronic device includes a silicon carbide layer including an n-type drift region therein, a contact forming a Schottky junction with the drift region, and...
US-9,466,673 Complementary metal-oxide silicon having silicon and silicon germanium channels
A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first...
US-9,466,672 Reduced defect densities in graded buffer layers by tensile strained interlayers
A semiconductor stack includes a substrate; a first semiconductor layer disposed on the substrate; a tensile strained interlayer layer disposed on the first...
US-9,466,671 Semiconductor device having fin gate, resistive memory device including the same, and method of manufacturing...
A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same are provided. The semiconductor device...
US-9,466,670 Sandwich epi channel for device enhancement
The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different...
US-9,466,669 Multiple channel length finFETs with same physical gate length
A semiconductor structure includes a first finFET device including a first fin, a first gate electrode structure on sidewalls and an upper surface of the first...
US-9,466,668 Inducing localized strain in vertical nanowire transistors
A device includes a semiconductor substrate and a vertical nano-wire over the semiconductor substrate. The vertical nano-wire includes a bottom source/drain...
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