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Patent # Description
US-9,466,617 Display panel and method of manufacturing the same
A display panel includes a first substrate, a first thin film transistor disposed on the first substrate, a color filter disposed on the first thin film...
US-9,466,616 Uniform junction formation in FinFETs
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel...
US-9,466,615 Semiconductor device
A semiconductor device that is suitable for miniaturization is provided. A semiconductor device including a first element, a first insulator over the first...
US-9,466,614 Vertically integrated memory cell
A vertically integrated memory cell including a deep trench extending into a substrate, a trench capacitor located within the deep trench, and a vertical...
US-9,466,613 Vertical type memory device
A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to...
US-9,466,612 Semiconductor memory devices and methods of forming the same
Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to...
US-9,466,611 Integrated circuit device and method for manufacturing the same
An integrated circuit device according to one embodiment includes a plurality of first electrode films stacked spaced from each other, a plurality of second...
US-9,466,610 Method of fabricating three-dimensional gate-all-around vertical gate structures and semiconductor devices, and...
Present example embodiments relate generally to methods of fabricating a three-dimensional gate-all-around (GAA) vertical gate (VG) semiconductor structure...
US-9,466,609 3-dimensional nonvolatile memory device and method of manufacturing the same
The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer...
US-9,466,608 Semiconductor structure having a dual-gate non-volatile memory device and methods for making same
A method for making a semiconductor structure includes forming an oxide layer onto non-volatile memory, high, and low voltage device regions of a substrate and...
US-9,466,607 Semiconductor integrated circuit and method of producing the same
Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the...
US-9,466,606 Semiconductor storage device
A semiconductor storage device according to an embodiment comprises stacks comprising insulating films and first wires that are alternately stacked....
US-9,466,605 Manufacturing method of non-volatile memory
A method of manufacturing a non-volatile memory is provided. A substrate including a first region and a second region is provided. A first patterning process is...
US-9,466,604 Metal segments as landing pads and local interconnects in an IC device
Methods for utilizing metal segments of an additional metal layer as landing pads for vias and also as local interconnects between contacts in an IC device and...
US-9,466,603 Semiconductor device with air gap and method for fabricating the same
A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring...
US-9,466,602 Embedded dynamic random access memory field effect transistor device
A method comprises forming a cavity in a substrate, depositing a silicon material in the cavity, forming a fin in the substrate and the silicon material such...
US-9,466,601 Semiconductor device and method of fabricating the same
A semiconductor device includes a substrate including first and second regions, a first transistor provided on the first region to include a first channel...
US-9,466,600 Semiconductor device and method of manufacturing the same
The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first metal gate...
US-9,466,599 Static current in IO for ultra-low power applications
An input/output (IO) circuit including: an IO driver circuit; an electrostatic discharge (ESD) protection semiconductor switch with a first input configured to...
US-9,466,598 Semiconductor structure suitable for electrostatic discharge protection application
A semiconductor structure suitable for ESD protection application is provided. The semiconductor structure includes a first well, a second well, a third well, a...
US-9,466,597 Chip package structure and chip packaging method
Embodiments of the present invention provide a chip package structure and a chip packaging method, which is related to the field of electronic technologies, and...
US-9,466,596 Geometry of MOS device with low on-resistance
A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region...
US-9,466,595 Fabrication of stacked die and structures formed thereby
Methods of forming a microelectronic structure are described. Those methods comprise forming a bond between a non-device side of a first die and a non-device...
US-9,466,594 Compact sensor module
A compact sensor module and methods for forming the same are disclosed herein. In some embodiments, a sensor die is mounted on a sensor substrate. A processor...
US-9,466,593 Stack semiconductor package
A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first...
US-9,466,592 Multi-chips in system level and wafer level package structure
A multi-chips in system level and wafer level package structure includes a package substrate having a plurality of through holes a multi-chips with different...
US-9,466,591 Semiconductor device
A semiconductor device includes a first semiconductor chip that includes a first main surface, a first inductor formed on the first main surface, and a first...
US-9,466,590 Optimized solder pads for microelectronic components
A multi-chip system includes a top chip stack element comprising a top chip having two major surfaces and top solder pads arrayed along a plane of one of the...
US-9,466,589 Power module package including heat spreader and inductance coil
There is provided a power module package. The power module package includes: a base substrate provided with a pattern; a heat spreader formed by being stacked...
US-9,466,588 Method and apparatus for multi-chip structure semiconductor package
A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally...
US-9,466,587 Multiple die in a face down package
A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing...
US-9,466,586 Method for manufacturing wafer-level fan-out package
Provided are a semiconductor package and a method for manufacturing a semiconductor package. The method for manufacturing a wafer-level fan-out package includes...
US-9,466,585 Reducing defects in wafer level chip scale package (WLCSP) devices
Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of...
US-9,466,584 Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes a first step of forming a first electrode on one main surface side of a semiconductor wafer; a second...
US-9,466,583 Semiconductor device
A semiconductor chip includes an electrode pad on a substrate, a barrier metal layer on the electrode pad, a bump electrode, a first protection layer formed on...
US-9,466,581 Semiconductor package device and manufacturing method thereof
A semiconductor device includes a die, a pad disposed on the die and configured to be electrically coupled with a bump through a conductive trace attached on...
US-9,466,580 Semiconductor package and manufacturing method thereof
A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a...
US-9,466,579 Reinforced structure for a stack of layers in a semiconductor component
The present application relates to a reinforcing structure for reinforcing a stack of layers in a semiconductor component, wherein at least one reinforcing...
US-9,466,578 Substrate comprising improved via pad placement in bump area
Some novel features pertain to an integrated device that includes a substrate, a first via, and a first bump pad. The first via traverses the substrate. The...
US-9,466,577 Semiconductor interconnect structure with stacked vias separated by signal line and method therefor
A semiconductor device is made by forming a first conductive layer over a substrate, forming a first passivation layer over the first conductive layer, forming...
US-9,466,576 Semiconductor device having features to prevent reverse engineering
An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the...
US-9,466,575 Semiconductor device
The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of...
US-9,466,574 Plasma-enhanced atomic layer deposition of conductive material over dielectric layers
Methods of forming a conductive metal layer over a dielectric layer using plasma enhanced atomic layer deposition (PEALD) are provided, along with related...
US-9,466,573 RF SOI switch with backside cavity and the method to form it
An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor...
US-9,466,572 Ultraviolet energy shield for non-volatile charge storage memory
An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing....
US-9,466,571 Systems and methods for high-speed, low-profile memory packages and pinout designs
Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit ("IC") package substrate capable of...
US-9,466,570 MOSFET with asymmetric self-aligned contact
A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a...
US-9,466,569 Though-substrate vias (TSVs) and method therefor
A semiconductor device includes a semiconductor substrate having a first major surface and a second major surface opposite the first major surface. A via...
US-9,466,568 Distributed on-chip decoupling apparatus and method using package interconnect
An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having...
US-9,466,567 Nanowire compatible E-fuse
An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy...
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