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Patent # Description
US-9,466,566 Stacked bit line dual word line nonvolatile memory
An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level...
US-9,466,565 Self-aligned contacts
A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate...
US-9,466,564 Semiconductor device and method for fabricating the same
A semiconductor device is disclosed. The semiconductor device includes: a substrate having a gate structure thereon and a first interlayer dielectric (ILD)...
US-9,466,563 Interconnect structure for an integrated circuit and method of fabricating an interconnect structure
An integrated circuit includes first and second metallization levels. The first metallization level includes a first metal routing path. The second ...
US-9,466,562 Semiconductor chip having plural penetration electrode penetrating therethrough
Disclosed herein is a semiconductor chip that includes: a plurality of penetration electrodes each penetrating between main and back surfaces of the...
US-9,466,561 Packaged semiconductor device for high performance memory and logic
A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a...
US-9,466,560 Interposer fabricating process and wafer packaging structure
An interposer fabricating process includes the following steps. A substrate, an oxide layer, and a dielectric layer are stacked from bottom to top, and an...
US-9,466,559 Semiconductor integrated circuit device
In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire...
US-9,466,558 Semiconductor device and method of manufacturing the same
According to one embodiment, a semiconductor device includes a semiconductor element, amounting substrate which has wiring layers containing copper, and a...
US-9,466,557 Electronic device with first and second contact pads and related methods
An electronic device may include leads, an IC having first and second bond pads, and an encapsulation material adjacent the leads and the IC so the leads extend...
US-9,466,556 Lead frame and semiconductor device
A lead frame includes an outer lead and a plating layer that covers a lower surface and side surfaces of the outer lead. The plating layer does not cover the...
US-9,466,555 Semiconductor chip and stack type semiconductor apparatus using the same
A semiconductor may include a core block configured to store and output data, and may be configured to output internal information. The semiconductor may...
US-9,466,554 Integrated device comprising via with side barrier layer traversing encapsulation layer
Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via...
US-9,466,553 Package structure and method for manufacturing package structure
Disclosed herein is a method for manufacturing a package structure. According to an exemplary embodiment of the present invention, the method for manufacturing...
US-9,466,552 Vertical semiconductor device having a non-conductive substrate and a gallium nitride layer
The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate...
US-9,466,551 Heat transferring clamp
The apparatus is a heat transferring clamp with a heat pipe connecting the clamp's stationary base part to each moveable clamping part. A connecting heat pipe...
US-9,466,550 Electronic device with redistribution layer and stiffeners and related methods
An electronic device may include an integrated circuit (IC), electrically conductive connectors coupled to the IC, and a heat sink layer adjacent the IC and...
US-9,466,549 Semiconductor module
A semiconductor module has a structure in which a semiconductor device, an insulating sheet, and a cooler are stacked on each other. The semiconductor device...
US-9,466,548 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device incorporating a heat spreader and improved to inhibit dielectric breakdown is provided. The semiconductor device has an electrically...
US-9,466,547 Passivation layer topography
A topographical structure is formed within an integrated circuit (IC) chip passivation layer. The topographical structure includes a trench extending below the...
US-9,466,546 Semiconductor device and method of forming the same
A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via...
US-9,466,545 Semiconductor package in package
A semiconductor package having a second semiconductor package or module integrated therein. The semiconductor package of the present invention typically...
US-9,466,544 Semiconducitive catechol group encapsulant adhesion promoter for a packaged electronic device
A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion...
US-9,466,543 Semiconductor package substrate, package system using the same and method for manufacturing thereof
A semiconductor package substrate includes an insulating substrate; a circuit pattern on the insulating substrate; a protective layer on the insulating...
US-9,466,542 Semiconductor device
A semiconductor device includes a semiconductor chip having a front electrode and a rear electrode; a conductive plate having a main surface connected to the...
US-9,466,541 Mechanism for MEMS bump side wall angle improvement
The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a...
US-9,466,540 Detecting apparatus, wafer and electronic device
Provided is a detection apparatus that detects process variation in a plurality of comparators that each output a comparison result obtained by comparing a...
US-9,466,539 Automated fillet inspection system with closed loop feedback and methods of use
Systems and methods for automated inspection of fillet formation along on or more peripheral edges (13a) of a packaged microelectronic device (14) that is...
US-9,466,538 Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process
A method of improving chip-to-chip alignment accuracy for circuitry-including wafer-to-wafer bonding. The method comprises providing separate stages for holding...
US-9,466,537 Method of inspecting semiconductor device and method of fabricating semiconductor device using the same
A method of inspecting a semiconductor device includes providing a substrate, on which a mold layer with a plurality of mold openings is provided, milling the...
US-9,466,536 Semiconductor-on-insulator integrated circuit with back side gate
Methods for manufacturing semiconductor-on-insulator (SOI) integrated circuits are disclosed. An SOI wafer is provided having a first surface and a second...
US-9,466,535 Method of forming target patterns
A method of forming target patterns is disclosed. A substrate with multiple fins is provided. A plurality of mask patterns is formed across the fins and in at...
US-9,466,534 Cointegration of directed self assembly and sidewall image transfer patterning for sublithographic patterning...
After forming transfer layer portions over a portion of a dielectric cap layer overlying a first portion of a substrate by a directed self-assembly process, a...
US-9,466,533 Semiconductor structure including a through electrode, and method for forming the same
A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned...
US-9,466,532 Micro-electro mechanical system (MEMS) structures with through substrate vias and methods of forming the same
The present disclosure includes micro-electro mechanical system (MEMS) structures and methods of forming the same. Substrates of the MEMS structures are bonded...
US-9,466,531 Apparatuses including stair-step structures and methods of forming the same
Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material,...
US-9,466,530 Methods of forming an improved via to contact interface by selective formation of a metal silicide capping layer
One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose...
US-9,466,529 Masking method for semiconductor devices with high surface topography
The method comprises the steps of providing a semiconductor body or substrate (1) with a recess or trench (2) in a main surface (10), applying a mask (3) on the...
US-9,466,528 Method of making a structure
A method of making a structure includes forming a first supporting member over a substrate, the first supporting member comprising a first material and having a...
US-9,466,527 Method for creating contacts in semiconductor substrates
Techniques include methods for creating contacts for microchips, solar films, etc., for electrically connecting conductive elements and/or for current...
US-9,466,526 Metal trench decoupling capacitor structure penetrating through a shallow trench isolation
A metal trench de-coupling capacitor structure includes a vertical trench disposed in a substrate, an insulating layer deposited on the sidewall of the vertical...
US-9,466,525 Interconnect structures comprising flexible buffer layers
A structure includes a substrate, a low-k dielectric layer over the substrate, and a conductive barrier layer extending into the low-k dielectric layer. The...
US-9,466,524 Method of depositing metals using high frequency plasma
Methods for depositing metal layers, and more specifically TaN layers, using CVD and ALD techniques are provided. In one or more embodiments, the method...
US-9,466,523 Contact hole collimation using etch-resistant walls
Contact holes are constrained to their designated active areas by etch-resistant walls so that they cannot contact adjacent active areas. Etch-resistant walls...
US-9,466,522 Method for fabricating semiconductor structure
A method for fabricating semiconductor structure is provided. A substrate having a plurality of blocks is provided. Each of the blocks includes a first region...
US-9,466,521 Semiconductor device having a patterned metal layer embedded in an interlayer dielectric layer
A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal...
US-9,466,520 Localized region of isolated silicon over recessed dielectric layer
An integrated circuit is formed by forming an isolation recess in a single crystal substrate which includes silicon, filling the isolation recess with isolation...
US-9,466,519 De-chuck control method and control device for plasma processing apparatus
A de-chuck control method is provided for de-chucking a workpiece from an electrostatic chuck, which includes a chuck electrode and electrostatically attracts...
US-9,466,518 Electrostatic chuck device
An electrostatic chuck device is provided in which there is no concern that a plate-shaped sample may be deformed when adsorbing the plate-shaped sample or when...
US-9,466,517 Microwave annealing apparatus and method of manufacturing a semiconductor device
According to one embodiment, a microwave annealing apparatus is provided, including a housing shielding electromagnetic waves, a first electromagnetic wave...
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