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Patent # Description
US-9,465,765 All-in-one SATA interface storage device
An all-in-one SATA interface storage device comprising: an interface board installed on a motherboard; a first memory card slot which is a CFast slot fixed on...
US-9,465,764 Interface extension device compatible with USB 2.0 and USB 3.0 standards
An interface extension device includes a USB port, a USB hub and a first interface conversion circuit. The USB hub has a first port connected to the USB port....
US-9,465,763 Bridge circuitry for communications with dynamically reconfigurable circuits
A bridge circuit may be used to interface between dynamically reconfigurable circuitry and dedicated circuitry or other circuitry having static configurations...
US-9,465,762 Communications control system with a serial communications interface and a parallel communications interface
A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of...
US-9,465,761 Managing slave devices
A hardware system comprises a digital signal generator, which generates a digital electrical signal that describes a first physical state of a first device; an...
US-9,465,760 Method and apparatus for delivering MSI-X interrupts through non-transparent bridges to computing resources in...
An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to...
US-9,465,759 Universal serializer architecture
Systems and methods for a universal Serializer-Deserializer (SerDes) architecture are described. In various implementations, a transceiver may include: a first...
US-9,465,758 Reconfigurable instruction cell array with conditional channel routing and in-place functionality
A reconfigurable instruction cell array is disclosed that includes an array of switch boxes. Each switch box within the array includes a set of I/O ports that...
US-9,465,757 Memory device with relaxed timing parameter according to temperature, operating method thereof, and memory...
A memory device used with a relaxed timing requirement specification according to temperatures, an operation method thereof, and a memory controller and a...
US-9,465,756 Configurable interconnection system
An interconnection system, apparatus and method is described where the motherboard may be populated with less than all of the modules that it has been designed...
US-9,465,755 Security parameter zeroization
Example embodiments disclosed herein relate to security parameter zeroization. Example embodiments include security parameter zeroization based on a remote...
US-9,465,754 Bridge circuit to arbitrate bus commands
A circuit may include a queue, a monitor, and a controller. The queue may receive and store a plurality of commands from a plurality of buses to access a shared...
US-9,465,753 Memory management unit that applies rules based on privilege identifier
A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on...
US-9,465,752 Systems and/or methods for policy-based access to data in memory tiers
Certain example embodiments provide efficient policy-based access to data stored in memory tiers, including volatile local in-process (L1) cache memory of an...
US-9,465,751 Efficient locking of memory pages
An apparatus is described that contains a processing core comprising a CPU core and at least one accelerator coupled to the CPU core. The CPU core comprises a...
US-9,465,750 Memory protection circuit, method and processing unit utilizing memory access information register to...
A memory protection circuit includes a memory access information register that stores memory access information related to memory areas which can be accessed by...
US-9,465,749 DMA engine with STLB prefetch capabilities and tethered prefetching
A system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for...
US-9,465,748 Instruction fetch translation lookaside buffer management to support host and guest O/S translations
A translation lookaside buffer (TLB) configured for use in a multiple operating system environment includes a plurality of storage locations, each storage...
US-9,465,747 Controller for controlling non-volatile memory and semiconductor device including the same
A controller controlling a non-volatile memory includes a first memory area suitable for storing a first address table, a second memory area suitable for...
US-9,465,746 Diagnostics for transactional execution errors in reliable transactions
Gathering diagnostics during a transactional execution in a transactional memory environment, a transactional memory environment for performing transactional...
US-9,465,745 Managing access commands by multiple level caching
Apparatus and associated method concerning managing access commands with a main storage space, a volatile buffer, and a nonvolatile buffer. The volatile buffer...
US-9,465,744 Data prefetch ramp implemenation based on memory utilization
A technique for data prefetching for a multi-core chip includes determining memory utilization of the multi-core chip. In response to the memory utilization of...
US-9,465,743 Method for accessing cache and pseudo cache agent
Embodiments of the present invention disclose a method for accessing a cache and a pseudo cache agent (PCA). The method of the present invention is applied to a...
US-9,465,742 Synchronizing barrier support with zero performance impact
The barrier-aware bridge tracks all outstanding transactions from the attached master. When a barrier transaction is sent from the master, it is tracked by the...
US-9,465,741 Multi processor multi domain conversion bridge with out of order return buffering
An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each...
US-9,465,740 Coherence processing with pre-kill mechanism to avoid duplicated transaction identifiers
An apparatus for processing coherency transactions in a computing system is disclosed. The apparatus may include a request queue circuit, a duplicate tag...
US-9,465,739 System, method, and computer program product for conditionally sending a request for data to a node based on a...
A system, method, and computer program product are provided for conditionally sending a request for data to a node based on a determination. In operation, a...
US-9,465,738 Information processing system, control method, program, and recording medium
An information processing system that determines whether static data is already loaded into shared memory when a request is made to load static data into shared...
US-9,465,737 Memory systems including a duplicate removing filter module that is separate from a cache module
A memory system includes a cache module configured to store data. A duplicate removing filter module is separate from the cache module. The duplicate removing...
US-9,465,736 Verification of management of real storage via multi-threaded thrashers in multiple address spaces
A method, system, and computer program product to verify management of real storage via multi-threaded thrashers in multiple address spaces are described. The...
US-9,465,735 System and method for uniform interleaving of data across a multiple-channel memory architecture with...
Systems and methods for uniformly interleaving memory accesses across physical channels of a memory space with a non-uniform storage capacity across the...
US-9,465,734 Coalition based memory management
One or more memory coalitions of software processes are created and used to decide whether to perform memory reduction operations on a data processing system....
US-9,465,733 Storage device and global garbage collection method of data storage system including the same
A storage device includes at least one nonvolatile memory device; and a memory controller configured to control the nonvolatile memory device, wherein the...
US-9,465,732 Binning of blocks for dynamic linking
A multi-plane non-volatile memory die includes circuits that receive and apply different parameters to different planes while accessing planes in parallel so...
US-9,465,731 Multi-layer non-volatile memory system having multiple partitions in a layer
A multi-layer memory and method for operation is disclosed. The memory includes multiple layers, where each layer includes flash memory cells having a greater...
US-9,465,730 Flash memory device
Different block management values that sequentially increase are set for a plurality of blocks to indicate active states of the blocks. For example, a first...
US-9,465,729 Memory allocation accelerator
Technologies are generally described for methods and systems effective to implement a memory allocation accelerator. A processor may generate a request for...
US-9,465,728 Memory controller adaptable to multiple memory devices
A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps...
US-9,465,727 Memory system, method for controlling the same, and information processing device
A memory system method for controlling the same, and an information processing device using the same are provided. The system includes a plurality of memory...
US-9,465,726 Abstract layer for automatic user interface testing
A method to provide automatic testing of a graphical user interface (GUI) having a plurality of GUI components includes maintaining an abstract layer configured...
US-9,465,725 Software defect reporting
Provided are approaches for software defect reporting. Specifically, one approach provides identifying a software defect; generating a software defect report,...
US-9,465,724 Method, program, and system for generating test cases
To provide a technique for generating, at a high speed, a smaller-sized set that satisfies an intended property such as, for example, being pair-wise, and...
US-9,465,723 Systems and/or methods for monitoring live software
Certain example embodiments described herein relate to techniques for observing an internal state of a software application executing in a runtime environment....
US-9,465,722 Error assessment tool
Embodiments of the invention are directed to a system, method, and computer program product for assessing error notifications associated with one or more...
US-9,465,721 Snapshotting executing code with a modifiable snapshot definition
A tracing and debugging system may take a snapshot of an application in response to an event, and may continue executing the program after the snapshot is...
US-9,465,720 Methods and systems for internally debugging code in an on-demand service environment
A remote debug session for a server group is provided. A server group including multiple servers that perform workload sharing receives a request to debug code...
US-9,465,719 Localized representation of stack traces
Systems and methods are disclosed for providing a representation of a stack trace. An example method includes identifying an element in a stack trace. The stack...
US-9,465,718 Filter generation for load testing managed environments
Automatic filter generation is used in a script for load testing a client application in a client/server managed environment. Filters are generated by recording...
US-9,465,717 Native code profiler framework
Embodiments provide systems, methods, and computer program products for dynamically hooking multiple levels of application code. A server receives identifying...
US-9,465,716 Run-time instrumentation directed sampling
The invention relates to implementing run-time instrumentation directed sampling. An aspect of the invention includes fetching a run-time instrumentation next...
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