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Patent # Description
US-9,473,187 Wireless radio extension using up- and down-conversion
A system may include a base station and a remote radio head ("RRH"). The base station may receive digital data streams destined for a user device, and generate...
US-9,473,186 Method of controlling receiver gain automatically and apparatus for automatic gain control in receiver
A method of controlling an automatic gain in a receiver includes receiving an input signal through an antenna of the receiver, by an automatic gain control unit...
US-9,473,185 Impedance matching for variable impedance antennas
An impedance matching circuit for a wireless communication device includes: a first node that receives a first impedance; a second node that is connected to an...
US-9,473,183 Antenna system calibration
A method for calibrating an antenna system (1) including a antenna elements (3) connected to signal receiver units (4) at an RF signal input port thereof...
US-9,473,182 Oportunistic interference cancellation of radar signals
In accordance with the exemplary embodiments there is at least a method and apparatus to operations including determining, by a communication device, parameters...
US-9,473,181 Digital combiner for phased-array RF receivers
Methods and systems for receiving radio frequency (RF) signals include adjusting a digital baseband signal from a first RF front-end to compensate for errors...
US-9,473,180 Apparatus for converting frequency and RF transmitter comprising same
Disclosed is an apparatus for converting a frequency. The apparatus includes: an oscillator configured to generate a first oscillation signal having a first...
US-9,473,179 Methods and apparatuses for LTE signal detection and classification by a Wi-Fi receiver
Methods, apparatuses, and computer program products for signal detection and classification are provided. One method includes detecting, by a station, a...
US-9,473,178 System and method for varying memory size in a data stream processing
The present disclosure relates to methods, systems, and computer-readable media for varying a memory size in a data stream processing while improving a...
US-9,473,177 Turbo decoder with a low-power input format and associated method
A turbo decoder stores received data in words in systematic memory and parity memory in a way that is known that it will be used for later iterations by turbo...
US-9,473,176 Implementation of log and inverse operation in a Galois Field
A method, including factoring an order of a multiplicative group of a Galois Field to produce a first integer factor p and a second integer factor q, wherein...
US-9,473,175 Forward error correction decoder system
Forward error correction (FEC) decoders, such as Low Density Parity Check (LDPC) decoders are described. Described FEC decoders minimize the number of internal...
US-9,473,174 Interleaving for layer-aware forward error correction
An error correcting encoder includes an error correcting data generator for receiving payload data belonging to a first category, for receiving payload data...
US-9,473,173 Method for early terminating decoding processes of serial concatenated coding and decoder using the same
A method and decoder for early terminating decoding processes of serial concatenated coding are disclosed. The method includes the steps of providing a...
US-9,473,172 Receiver deserializer latency trim
A system and method for receiving includes an input multiplexer configured to select between one or more input data streams and a pseudo random bit sequence...
US-9,473,171 Data encoding method for compressing data to be stored, data storage device with data encoder, and operating...
Provided is a data encoding method such that memory cells storing the data form a biased threshold voltage distribution. The data encoding method may include...
US-9,473,170 Entropy coding of motion vector differences
An entropy decoder is configured to, for horizontal and vertical components of motion vector differences, derive a truncated unary code from the data stream...
US-9,473,169 Entropy encoding and decoding scheme
Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective...
US-9,473,168 Systems, methods, and apparatuses for compression using hardware and software
Detailed herein are embodiments of systems, methods, and apparatuses for compression using hardware and software. Embodiments include compressor hardware to...
US-9,473,167 Pad encoding and decoding
A system, method and computer program product for encoding an input string of binary characters representing alphanumeric characters. A system includes: a...
US-9,473,166 Analog-to-digital converter and an image sensor including the same
An analog-to-digital converter includes a modulator, a controller, and a digital filter. The modulator generates a modulated signal based on an analog signal....
US-9,473,165 Reducing signal dependence for CDAC reference voltage
Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a...
US-9,473,164 Method for testing analog-to-digital converter and system therefor
A data processing system having an analog-to-digital converter (ADC) and method for testing the ADC are provided. The data processing system also comprises a...
US-9,473,163 Preamplifier circuit and SAR ADC using the same
A preamplifier circuit comprising six transistors is provided. The first transistor is coupled to a power supply line and the second transistor is coupled to a...
US-9,473,162 Method for digital error correction for binary successive approximation analog-to-digital converter (ADC)
An analog input voltage is converted to a digital code by, generating a first set of confirmed bits based on a first series of comparisons of an output of a...
US-9,473,161 Mixed signal automatic gain control for increased resolution
A combination of a precision analog-to-digital converter (ADC), an analog amplifier having selectable gains and an intelligent controller to coordinate the...
US-9,473,160 Method and device for analog/digital conversion of an analog signal
A method includes a first analog/digital conversion of an analog signal over m bits, with m less than n, associated with a first full-scale value, and a second...
US-9,473,159 Method and apparatus for performing analog-to-digital conversion on multiple input signals
A method, computer-readable storage medium, and signal processing apparatus for processing a plurality of input signals. The method includes receiving or...
US-9,473,158 Radio frequency receiver with overlapped analog to digital converter (ADC) architecture
A radio frequency receiver includes a first and second analog to digital converter (ADC) connected in parallel. Each ADC is coupled to a corresponding mixer...
US-9,473,157 Frequency synthesizer with injection pulling/pushing suppression/mitigation and related frequency synthesizing...
A frequency synthesizer includes a phase-locked loop (PLL) and a loop bandwidth controller. The PLL generates an output clock according to a reference clock....
US-9,473,156 Fast settling phase locked loop (PLL) with optimum spur reduction
A method for constructing a phase locked loop begins with determining spurious frequency component criteria permitted within the PLL. A PLL filter prototype is...
US-9,473,155 Software reconfigurable digital phase lock loop architecture
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit...
US-9,473,154 Semiconductor device and phase locked loop including the same
Provided are a semiconductor device and a phase-locked loop (PLL) including the same. The semiconductor device including an output node from which an output...
US-9,473,153 Oscillation circuit, oscillator, electronic device, and moving object
An oscillation circuit, an oscillator, an electronic device and a moving object, having at least a serial interface and an output enabling function, which are...
US-9,473,152 Coupling structure for inductive device
A circuit includes a coupling structure and a first inductive device. The coupling structure includes two or more conductive loops and a set of conductive paths...
US-9,473,151 Low-noise oscillator amplitude regulator
A frequency generation solution controls an oscillator amplitude using two feedback paths to generate high frequency signals with lower power consumption and...
US-9,473,150 Peak detectors for amplitude control of oscillators
Various techniques for automatic amplitude control of an oscillator are described. An apparatus includes an oscillator circuit configured to generate an...
US-9,473,149 Temperature-compensated signal generator for supply voltage monitoring
A signal generator configured to generate an oscillating signal with a temperature-compensated frequency. The signal generator includes a ring oscillator, and a...
US-9,473,148 Method for compensating local oscillator frequency
An oscillator circuit includes a voltage-controlled oscillator configured to output an AC output signal having a predetermined frequency, which changes due to...
US-9,473,147 Frequency dividing apparatus and related method
A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency...
US-9,473,146 Apparatuses and methods for low power counting circuits
Apparatuses and methods for low power counting circuits are described herein. An example apparatus may include a frequency divider configured to receive an...
US-9,473,145 Programmable high-speed I/O interface
Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a...
US-9,473,144 Integrated circuit device with programmable analog subsystem
An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable...
US-9,473,143 Driving circuit for generating voltage control signals
A driving circuit includes an activating end, an operation switch, a voltage control end, and an output switch. The activating end selectively outputs a first...
US-9,473,142 Method for performing signal driving control in an electronic device with aid of driving control signals, and...
A method for performing signal driving control in an electronic device and an associated apparatus are provided. The method includes: generating a first driving...
US-9,473,141 Receiving an I/O signal in multiple voltage domains
Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O...
US-9,473,140 Series arranged multiplexers specification support enablement circuit and method
Several circuits and methods that may be implemented to enable specification support of a plurality of interface components in an IC are disclosed. In an...
US-9,473,139 Threshold logic element with stabilizing feedback
Threshold logic elements and methods of operating the same are disclosed. In one embodiment, a threshold logic element includes a first input gate network...
US-9,473,138 Crosstalk compensation circuit
Embodiments include apparatuses, methods, and systems for crosstalk compensation. In embodiments, a transmitter may include a crosstalk compensation circuit...
US-9,473,137 Non-volatile boolean logic operation circuit and operation method thereof
A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M.sub.1, the first resistive...
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