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Patent # Description
US-9,472,685 Methods of circuit construction to improve diode performance
The present invention is a method by which diodes are connecting in a circuit such that they are more robust. The method involves placing two diodes of opposite...
US-9,472,684 Lateral GaN JFET with vertical drift region
A gallium nitride (GaN)-based junction field-effect transistor (JFET) can include a GaN drain region having a top surface extending in a lateral dimension, a...
US-9,472,683 Field effect transistor
An insulating film is provided over one surface of a first semiconductor layer including a first oxide semiconductor including indium as a main component, and a...
US-9,472,682 Semiconductor device and method for manufacturing semiconductor device
In a top-gate transistor in which an oxide semiconductor film, a gate insulating film, a gate electrode layer, and a silicon nitride film are stacked in this...
US-9,472,681 Semiconductor device and method for manufacturing the same
The electrical characteristics of a transistor including an oxide semiconductor layer are varied by influence of an insulating film in contact with the oxide...
US-9,472,680 Semiconductor device
A semiconductor device includes a first transistor which includes a first gate electrode below its oxide semiconductor layer and a second gate electrode above...
US-9,472,679 Semiconductor device
A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer...
US-9,472,678 Semiconductor device
To provide a transistor with stable electrical characteristics, a transistor with a low off-state current, a transistor with a high on-state current, a...
US-9,472,677 Semiconductor device
A semiconductor device including an oxide semiconductor can have stable electric characteristics and high reliability. A transistor in which an oxide...
US-9,472,676 Semiconductor device and manufacturing method thereof
A semiconductor device having excellent electric characteristics and a method for manufacturing the semiconductor device are provided. A method for...
US-9,472,675 Method of manufacturing n-doped graphene and electrical component using NH.sub.4F, and graphene and electrical...
This disclosure relates to a method of manufacturing n-doped graphene and an electrical component using ammonium fluoride (NH.sub.4F), and to graphene and an...
US-9,472,674 Thin film transistor with two gates protruding from scan line under a double-layer channel
A thin film transistor includes a first gate electrode located on a base, a second gate electrode located on the base, an insulating layer, a source electrode,...
US-9,472,673 Thin film transistor, method of manufacturing same, and image display apparatus
A source electrode (5) and a drain electrode (6) are film-formed, and a semiconductor layer (7) is formed in a substantially stripe shape substantially parallel...
US-9,472,672 Eliminating fin mismatch using isolation last
An embodiment fin field-effect transistor (FinFET) includes an inner fin, and outer fin spaced apart from the inner fin by a shallow trench isolation (STI)...
US-9,472,671 Method and structure for forming dually strained silicon
A semiconductor structure and method for fabricating such. The semiconductor structure includes a monolithic substrate, a first dielectric layer carried by the...
US-9,472,670 Field effect transistor device spacers
A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin,...
US-9,472,669 Semiconductor Fin FET device with epitaxial source/drain
In a method of fabricating a Fin FET, first and second fin structures are formed. The first and second fin structures protrude from an isolation insulating...
US-9,472,668 Semiconductor device and fabrication method thereof
The present disclosure provides a semiconductor fabrication method. The method includes providing a semiconductor substrate having first regions and second...
US-9,472,667 III-V MOSFET with strained channel and semi-insulating bottom barrier
Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a...
US-9,472,666 Ultra high voltage device
According to an embodiment, a semiconductor device is provided. The device includes: The second region has a greater curvature than the first region. The device...
US-9,472,665 MOS transistor and method for manufacturing MOS transistor
A novel MOS transistor, which includes a source region, a drain region, a channel region, an isolation region, a drift region, a gate dielectric layer, a gate...
US-9,472,664 Semiconductor device and manufacturing method thereof
The present disclosure provides a semiconductor device including a substrate, a gate structure, a channel layer, a first active region and a second active...
US-9,472,663 N-type field effect transistors, arrays comprising N-type vertically-oriented transistors, methods of forming...
An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region...
US-9,472,662 Bidirectional power transistor with shallow body trench
A bi-directional trench field effect power transistor. A layer stack extends over the top surface of the substrate, in which vertical trenches are present. An...
US-9,472,661 Semiconductor structure
A semiconductor structure suitable for operating under a high voltage condition is provided. According to one aspect of the disclosure, the semiconductor...
US-9,472,660 Semiconductor device
A semiconductor device including: a first conductivity type n-type drift layer; a second conductivity type VLD region which is formed on a chip inner...
US-9,472,659 Semiconductor devices
Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant...
US-9,472,658 III-V nanowire FET with compositionally-graded channel and wide-bandgap core
A method for fabricating a III-V nanowire. The method may include providing a semiconductor substrate, which includes an insulator, with a wide-bandgap layer on...
US-9,472,657 Triode
A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a p+ doping region. The deep n-well is disposed adjacent to the...
US-9,472,656 Semiconductor device and method for manufacturing the same
A semiconductor device including a minute transistor with a short channel length is provided. A gate insulating layer is formed over a gate electrode layer; an...
US-9,472,655 Method for producing a semiconductor device
An improvement is made in the reliability of a semiconductor device having a split gate type MONOS memory. An ONO film covering a control gate electrode, and a...
US-9,472,654 Forming low parasitic trim gate last MOSFET
A method for making a fin MOSFET with substantially reduced parasitic capacitance and/or resistance is provided. The fin MOSFET includes: a patterned fin...
US-9,472,653 Method for fabricating semiconductor device
A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is...
US-9,472,652 Fin structure of semiconductor device
The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure...
US-9,472,651 Spacerless fin device with reduced parasitic resistance and capacitance and method to fabricate same
A structure includes a substrate having an insulator layer and a plurality of elongated semiconductor fin structures disposed on a surface of the insulator...
US-9,472,650 Manufacturing method of flexible display device
A method of manufacturing a flexible display device, the method including forming a sacrificial layer on a carrier substrate such that the sacrificial layer...
US-9,472,649 Fabrication method for multi-zoned and short channel thin film transistors
A method of fabricating a multi-zone, short gate length thin film transistor is provided. Gate metal and a plurality of layers are deposited on a substrate. The...
US-9,472,648 Semiconductor device, printing apparatus, and manufacturing method thereof
A manufacturing method of a semiconductor device including a DMOS transistor, an NMOS transistor and a PMOS transistor arranged on a semiconductor substrate,...
US-9,472,647 Source/drain structure of semiconductor device
The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a...
US-9,472,646 Dual work function buried gate type transistor and method for fabricating the same
A transistor includes a substrate having an active region defined by an isolation layer; a first trench defined in the active region and a second trench defined...
US-9,472,645 Dual control gate spacer structure for embedded flash memory
The present disclosure relates to a split gate flash memory cell. In some embodiments, the split gate flash memory cell has a select gate separated from a...
US-9,472,644 Semiconductor device with air gap and method for fabricating the same
A method for fabricating a semiconductor device includes forming a gate structure over a substrate, forming a multi-layer sidewall spacer including a first...
US-9,472,643 Method to improve reliability of replacement gate device
A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k...
US-9,472,642 Method of forming a semiconductor device structure and such a semiconductor device structure
The present disclosure provides in one aspect for a semiconductor device structure which may be formed by providing source/drain regions within a semiconductor...
US-9,472,641 Ambipolar synaptic devices
Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either...
US-9,472,640 Self aligned embedded gate carbon transistors
Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a...
US-9,472,639 Forming a liquid ejection head with through holes and a depression
A method of manufacturing a substrate of a liquid ejection head including: forming a plurality of recesses in a silicon wafer; etching the silicon wafer with...
US-9,472,638 FinFETs with multiple threshold voltages
A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A...
US-9,472,637 Semiconductor device having electrode made of high work function material and method of manufacturing the same
Provided is a semiconductor device including a metal film which can be formed with lower costs but still mange to have a necessary work function and oxidation...
US-9,472,636 Cost-effective gate replacement process
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure...
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