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Phototransistor and semiconductor device
A phototransistor includes a first emitter region, a first base region having at least a portion exposed to a light-receiving side, and a first collector region...
Method of manufacturing display apparatus using etching buffer layer
A method of manufacturing a display device including providing a substrate, forming a semiconductor layer on the substrate, forming a first insulating layer on...
Thin film transistor array panel and manufacturing method thereof
A thin film transistor array panel includes an insulation substrate; a gate line and a data line on the insulation substrate; a first passivation layer on the...
A display device according to an exemplary embodiment of the present invention includes: a first insulation substrate; a thin film transistor disposed on the...
Pixel array and display panel
A pixel array and a display panel are provided. The pixel array includes a plurality of pixel units. Each of the pixel units includes a first scan line, a...
Array substrate with improved pad region
An array substrate having a wiring of a pad region formed without an insulating film or without an insulating film and an organic film to reduce abnormal...
Display substrate and fabricating method thereof, display panel, and
The present invention provides a display substrate and a fabricating method thereof, a display panel, and a display device. The display substrate comprises a...
Thin film transistor substrate, display apparatus having the same, and
manufacturing method thereof
Each pixel of a thin film transistor substrate includes a base substrate including a pixel display area and a pixel non-display area surrounding the pixel...
Structure and method to reduce crystal defects in epitaxial fin merge
using nitride deposition
A FinFET device includes a substrate with a buried insulator, a plurality of fins over the buried insulator, and a nitride material filing spaces between the...
Formation of strained fins in a finFET device
In an aspect of the present invention, a field-effect transistor (FET) structure is formed. The FET structure comprises a plurality of fins formed on a...
Ultrathin body (UTB) FinFET semiconductor structure
For fabrication of a semiconductor structure, there is set forth herein a method of fabricating a semiconductor structure, the method including forming a...
Silicon-germanium fin formation
Forming a set of semiconductor fins is disclosed. Forming the set of semiconductor fins can include forming a base structure including a silicon substrate, an...
Fin field effect transistor (finFET) device including a set of merged fins
formed adjacent a set of unmerged fins
Approaches for simultaneously providing a set of merged and unmerged fins in a fin field effect transistor device (FinFET) are disclosed. In at least one...
Isolated semiconductor layer over buried isolation layer
An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of...
Diode biased body contacted transistor
Approaches for body contacted transistors are provided. A method of manufacturing a semiconductor structure includes forming a field effect transistor (FET)...
Method of manufacturing a double-source semiconductor device
A semiconductor device may include a first source layer, a first insulating layer located over the first source layer, and a first stacked structure located...
Semiconductor device and method of fabricating the same
A semiconductor device is provided as follows. A peripheral circuit structure is disposed on a first substrate. A cell array structure is disposed on the...
Semiconductor device having three-dimensional structure and method of
manufacturing the same
A semiconductor device includes a semiconductor pattern; conductive layers each including a first portion through which the semiconductor pattern passes and a...
Semiconductor device and method of manufacturing the same
A semiconductor device may include a substrate provided in a peripheral region, first and second insulation pillars formed in the substrate, and a gate...
Non-volatile memory device
A non-volatile memory device includes: a floating gate having a plurality of fingers; a first coupling unit including an active control gate which overlaps with...
System with memory having voltage applying unit
The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of...
Semiconductor device and fabrication method therefor
A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor...
Semiconductor device and method for fabricating the same
A semiconductor device includes a substrate, a plurality of memory cells, a logic gate electrode and a high-voltage gate electrode. The substrate at least...
Manufacturing method for semi-floating gate device
A manufacturing method for a semi-floating gate device, mainly comprising a manufacturing method for a floating gate and a floating gate opening area, and the...
Memory cell and an array of memory cells
A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and...
Memory device and semiconductor device
It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching...
Semiconductor structures with stacked non-planar field effect transistors
and methods of forming the structures
Disclosed are semiconductor structures and methods of forming them. The structures include field effect transistors (FETs) with different type conductivities in...
Memory transistors with buried gate electrodes
A device includes a semiconductor region surrounded with the isolation region and includes a first active region, a channel region and a second active region...
SOI lateral bipolar for integrated-injection logic SRAM
A static random access memory (SRAM) cell is provided. The SRAM cell consists of two cross coupled integrated-injection logic (I.sup.2L) inverter devices. Each...
Nanosheet CMOS with hybrid orientation
A semiconductor structure is provided that includes a substrate comprising a first semiconductor material having a first crystallographic orientation and a...
Integrated circuits having FinFET semiconductor devices and methods of
fabricating the same to resist sub-fin...
Integrated circuits that have a FinFET and methods of fabricating the integrated circuits are provided herein. In an embodiment, a method of fabricating an...
High-K gate dielectric and metal gate conductor stack for planar field
effect transistors formed on type III-V...
An electrical device that includes a substrate including a first region of a type III-V semiconductor material and a second region of a type IV germanium...
CMOS devices having dual high-mobility channels
A method for forming a semiconductor structure includes providing a semiconductor substrate including a first region and a second region; and forming a first...
Vertical CMOS structure and method
A method for forming stacked, complementary transistors is disclosed. Selective deposition techniques are used to form a column having a lower portion that...
Adjusted fin width in integrated circuitry
A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite...
Cascoded semiconductor devices
A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide FET to provide avalanche...
Reverse conducting semiconductor device
A reverse conducting semiconductor device includes a high-concentration anode layer and a barrier metal layer, the width of the high-concentration anode layer...
A power element and a temperature sensing element are formed on the same semiconductor substrate, and one end of a PN junction of the temperature sensing...
Cell-based IC layout system and cell-based IC layout method
A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal...
Semiconductor arrangement with electrostatic discharge (ESD) protection
One or more semiconductor arrangements having a stacked configuration and electrostatic discharge (ESD) protection are provided. The semiconductor arrangements...
Semiconductor device comprising electrostatic discharge protection
A semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device...
Wide band gap semiconductor device
The present invention includes a second source layer formed on a surface layer of a p base layer in the same step as that of forming a n.sup.+ source layer to...
DRAM arrays, semiconductor constructions and DRAM array layouts
Some embodiments include a DRAM array layout. Wordlines extend along a first direction, and bitlines extend along a second direction that crosses the first...
Methods for manufacturing an electronic module
A method for manufacturing an electronic module is disclosed. In an embodiment the method includes providing a passive component having an upper surface of a...
Methods for making semiconductor device with sealing resin
Various embodiments of the present invention include a method for making a semiconductor device the method including disposing a first semiconductor chip on a...
Semiconductor chip and a semiconductor package having a package on package
(POP) structure including the...
A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the...
Semiconductor device manufacturing method and semiconductor device
Fixing a semiconductor element to a substrate, electrically connecting signal and main terminals to the semiconductor element, a terminal aggregate includes a...
Semiconductor device and method for manufacturing the same
A semiconductor device includes first, second, and third molded bodies. The first molded body covers a first light emitting element, a part of a lead...
Strain tunable light emitting diodes with germanium P-I-N heterojunctions
Tunable p-i-n diodes comprising Ge heterojunction structures are provided. Also provided are methods for making and using the tunable p-i-n diodes. Tunability...
Method of arranging a multiplicity of LEDs in packaging units, and
packaging unit including a multiplicity of LEDs
A method of arranging a multiplicity of LEDs in packaging units includes defining a desired range for at least one photometric measurement variable for each of...