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Patent # Description
US-9,472,533 Semiconductor device and method of forming wire bondable fan-out EWLB package
A semiconductor device has a first semiconductor die and a first encapsulant deposited over the first semiconductor die. An interconnect structure is formed...
US-9,472,532 Leadframe area array packaging technology
Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured...
US-9,472,531 Device packaging facility and method, and device processing apparatus utilizing phthalate
Provided are a device packing facility and method using phthalate and a device processing apparatus utilizing the phthalate. The device packaging facility...
US-9,472,530 Method for carrying out a conductive direct metal bonding
A method includes a) Providing a first substrate covered by a metal layer and a second substrate covered by a metal layer, b) Bringing into direct contact the...
US-9,472,529 Apparatus and methods for high-density chip connectivity
An electronic circuit and method may include a first chip including first electronics and a first connector including multiple self-alignment features and...
US-9,472,528 Integrated electronic package and method of fabrication
An integrated electronic package includes an integrated circuit (IC) die and conductive discrete components. Electrical interconnects are formed directly...
US-9,472,527 Semiconductor device and manufacturing method thereof
Surfaces of a semiconductor chip and a circuit board are made to face each other, and upper portions of stoppers of the circuit board are fit into regions...
US-9,472,526 Semiconductor device with external connection bumps
A semiconductor device includes a main structure, active bumps and dummy bumps which are provided over a surface of the main structure. The active bumps are...
US-9,472,525 Bump-on-trace structures with high assembly yield
A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace...
US-9,472,524 Copper-containing layer on under-bump metallization layer
A semiconductor device includes an under-bump metallization (UBM) layer over a substrate. The semiconductor device also includes a copper-containing layer...
US-9,472,523 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a conductive bump for disposing over a substrate and an elongated ferromagnetic member surrounded by the conductive bump,...
US-9,472,522 Packaging devices and methods of manufacture thereof
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad...
US-9,472,521 Scheme for connector site spacing and resulting structures
A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the...
US-9,472,520 Multilayer pillar for reduced stress interconnect and method of making same
A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar...
US-9,472,519 Forming sacrificial composite materials for package-on-package architectures and structures formed thereby
Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a...
US-9,472,518 Semiconductor structures including carrier wafers and methods of using such semiconductor structures
A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars...
US-9,472,517 Dry-removable protective coatings
Techniques are disclosed for protecting a surface using a dry-removable protective coating that does not require chemical solutions to be removed. In an...
US-9,472,516 Fan out package structure and methods of forming
An embodiment is a structure comprising a die having a pad on a surface and an encapsulant at least laterally encapsulating the die. The pad is exposed through...
US-9,472,515 Integrated circuit package
Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing...
US-9,472,514 Methods to fabricate a radio frequency integrated circuit
To reduce radio frequency (RF) losses during operation of a radio frequency integrated circuit (RFIC) module, the RFIC module is fabricated such that at least...
US-9,472,513 Transmission line for 3D integrated circuit
A semiconductor transmission line substructure and methods of transmitting RF signals are described. The semiconductor transmission line substructure can...
US-9,472,512 Integrated circuits with contacts through a buried oxide layer and methods of producing the same
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate, where the substrate...
US-9,472,511 ESD clamp with a layout-alterable trigger voltage and a holding voltage above the supply voltage
An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed...
US-9,472,510 Semiconductor device and control system
To enhance the security of a semiconductor device, the semiconductor device has a regulator unit for generating an internal power supply voltage based on a...
US-9,472,509 Dummy metal structure and method of forming dummy metal structure
Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal...
US-9,472,508 Interconnect arrangement with stress-reducing structure and method of fabricating the same
A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection...
US-9,472,507 Array substrate and organic light-emitting display including the same
An array substrate includes a substrate, a barrier layer disposed on the substrate, a buffer layer disposed on the barrier layer, a first insulating layer...
US-9,472,506 Registration mark formation during sidewall image transfer process
Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may...
US-9,472,505 Die or substrate marking using a laser
Apparatus, systems, and methods are provided to generate markings on the surface of a die or substrate. The markings represent information. The markings can be...
US-9,472,504 Semiconductor having a high aspect ratio via
The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having...
US-9,472,503 Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low...
An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting...
US-9,472,502 Cobalt interconnect techniques
Some embodiments relate to a method of manufacturing an integrated circuit device. In this method a dielectric layer is formed over a substrate. The dielectric...
US-9,472,501 Conductive line patterning
A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The...
US-9,472,500 Nonvolatile memory devices having single-layered gates
A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending...
US-9,472,499 Self-aligned pitch split for unidirectional metal wiring
Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a...
US-9,472,498 Multiple access over proximity communication
A multiple access Proximity Communication system in which electrical elements on an integrated circuit chip provide the multiplexing of multiple signals to a...
US-9,472,497 Semiconductor device
A semiconductor device is disclosed. The semiconductor comprises a field effect transistor (FET) provided in a substrate, the FET including a plurality of...
US-9,472,495 Semiconductor device and method of manufacturing the same
Possible to form an opening having a sufficient opening diameter in a region sandwiched between a pair of bit lines and thereby provide a semiconductor device...
US-9,472,494 Lead frame for semiconductor device
Provided is a lead frame for a semiconductor device, which includes a base layer made of copper, a strike plating layer or a self assembly monolayer (SAM),...
US-9,472,493 High heat-dissipation chip package structure
A high heat-dissipation chip package structure for packaging the semiconductor chips is disclosed. A pre-attachment film is adhered on an upper surface of a...
US-9,472,492 Semiconductor device with lead terminals having portions thereof extending obliquely
A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The...
US-9,472,491 Semiconductor package with small gate clip and assembly method
A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source...
US-9,472,490 IC structure with recessed solder bump area and methods of forming same
Embodiments of the present disclosure provide an integrated circuit (IC) structure with a recessed solder bump area, and methods of forming the same. An IC...
US-9,472,489 Heat exchanger
An inner fin is provided in a fluid pipe for dividing a fluid passage for heating medium into multiple small fluid passages, so as to facilitate heat exchange...
US-9,472,488 Semiconductor device and cooler thereof
A semiconductor device exhibits low pressure loss and is capable of cooling a plurality of power semiconductor chips evenly. This semiconductor device includes...
US-9,472,487 Flexible electronic package integrated heat exchanger with cold plate and risers
In some embodiments, a semiconductor cooling apparatus includes a heat exchanger configured to thermally couple to a semiconductor element to transfer heat to...
US-9,472,486 Circuit device and method of manufacturing a circuit device for controlling a transmission of a vehicle
A circuit device for controlling a transmission of a vehicle comprises an integrated circuit, which is mounted with a first surface on a first support surface...
US-9,472,485 Hybrid thermal interface material for IC packages with integrated heat spreader
Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is...
US-9,472,484 Semiconductor structure having thermal backside core
A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes...
US-9,472,483 Integrated circuit cooling apparatus
A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a...
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