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Patent # Description
US-9,472,482 Semiconductor device
A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering...
US-9,472,481 Packages with stress-reducing structures and methods of forming same
A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the...
US-9,472,480 Over-mold packaging for wide band-gap semiconductor devices
A transistor package includes a lead frame and a gallium nitride (GaN) transistor attached to the lead frame. The lead frame and the GaN transistor are...
US-9,472,479 Methods and apparatus for providing an interposer for interconnecting semiconductor chips
Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package,...
US-9,472,478 Die testing using top surface test pads
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding...
US-9,472,477 Electromigration test structure for Cu barrier integrity and blech effect evaluations
An electromigration test structure is provided for evaluation of interconnect liner integrity in a semiconductor interconnect structure. The electromigration...
US-9,472,476 System and method for test structure on a wafer
System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing an integrated circuit....
US-9,472,475 Feedback control using detection of clearance and adjustment for uniform topography
A method of controlling polishing includes storing a desired ratio representing a ratio for a clearance time of a first zone of a substrate to a clearance time...
US-9,472,474 Methods for characterizing shallow semiconductor junctions
The disclosed technology generally relates to methods of characterizing semiconductor materials, and more particularly to methods of characterizing shallow...
US-9,472,473 Method and device for testing a thin film transistor
A method and device for testing a thin film transistor (TFT) provided on an array substrate are provided in an embodiment. The method comprises determining...
US-9,472,472 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first main surface side of the first semiconductor...
US-9,472,471 Hybrid orientation vertically stacked III-V and Ge gate-all-around CMOS
A method of CMOS construction may include stacked III-V nanowires and stacked Ge nanowires. The CMOS construction may include a hybrid orientation with surface...
US-9,472,470 Methods of forming FinFET with wide unmerged source drain EPI
A method including forming fin spacers on opposite sidewalls of a semiconductor fin made from a semiconductor substrate, forming a dielectric layer in direct...
US-9,472,469 Back gate in select transistor for eDRAM
This disclosure relates to an eDRAM memory element comprising a first storage node, a bitline node for accessing the value stored in the storage node, and a...
US-9,472,468 Nanowire CMOS structure and formation methods
A method includes growing a nanowire from a substrate, forming a sacrificial layer surrounding the nanowire, removing the nanowire from the sacrificial layer to...
US-9,472,467 Manufacturing method of semiconductor device
A method of forming a semiconductor device including a semiconductor substrate having a first surface and a second surface, and having a gallium...
US-9,472,466 Semiconductor device having reduced-damage active region and method of manufacturing the same
A semiconductor device according to example embodiments may include a substrate having an NMOS area and a PMOS area, isolation regions and well regions formed...
US-9,472,465 Methods of fabricating integrated circuits
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method is provided for fabricating an integrated circuit....
US-9,472,464 Methods to utilize merged spacers for use in fin generation in tapered IC devices
Methods for processes to form and use merged spacers in fin generation and the resulting devices are disclosed. Embodiments include providing first and second...
US-9,472,463 Patterning process for Fin implantation
After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is...
US-9,472,462 Method of manufacturing 3D semiconductor integrated circuit device
A method of manufacturing a semiconductor integrated circuit device is provided. The method includes forming a plurality of pillars in a semiconductor...
US-9,472,461 Double gated 4F2 dram CHC cell and methods of fabricating the same
A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein...
US-9,472,460 Uniform depth fin trench formation
Methods for forming substantially uniform depth trenches and/or semiconductor fins from the trenches are disclosed. Embodiments of the method may include...
US-9,472,459 Wafer divider and wafer division method
A divider which divides a wafer having a division start points formed along the scheduled divisions into a plurality of device chips. The divider includes a...
US-9,472,458 Method of reducing residual contamination in singulated semiconductor die
In one embodiment, semiconductor die are singulated from a semiconductor wafer by placing the semiconductor wafer onto a carrier tape, forming singulation lines...
US-9,472,457 Manganese oxide hard mask for etching dielectric materials
A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be...
US-9,472,456 Technology for selectively etching titanium and titanium nitride in the presence of other materials
Methods for selectively etching titanium and titanium nitride are disclosed. In some embodiments the method involve exposing a workpiece to a first solution to...
US-9,472,455 Methods of cross-coupling line segments on a wafer
A method is provided for fabricating cross-coupled line segments on a wafer for use, for instance, in fabricating cross-coupled gates of two or more...
US-9,472,454 Tungsten film forming method
In a tungsten film forming method, a substrate having a recess is provided in a processing chamber, and a first tungsten film is formed on the substrate to fill...
US-9,472,453 Systems and methods of forming a reduced capacitance device
A method includes forming an electronic device structure including a substrate, an oxide layer, and a first low-k layer. The method also includes forming...
US-9,472,452 Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of...
A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer...
US-9,472,451 Technique for wafer-level processing of QFN packages
Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In...
US-9,472,450 Graphene cap for copper interconnect structures
Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is...
US-9,472,449 Semiconductor structure with inlaid capping layer and method of manufacturing the same
A method of fabricating a semiconductor structure includes forming a dielectric layer overlaying a substrate; forming a trench in the dielectric layer; forming...
US-9,472,448 Contact plug without seam hole and methods of forming the same
A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the...
US-9,472,447 Confined eptaxial growth for continued pitch scaling
A technique relates to manufacturing a finFET device. A plurality of first and second semiconductor fins are formed on a substrate. Gate stacks are formed on...
US-9,472,446 Methods of forming a FinFET semiconductor device with a unique gate configuration, and the resulting FinFET device
One method disclosed includes, among other things, forming an overall fin structure having a stepped cross-sectional profile, the fin structure having an upper...
US-9,472,445 Semiconductor memory device and method of fabricating the same
A semiconductor memory device including a substrate, a first element isolation film pattern, and a second element isolation film pattern. The substrate includes...
US-9,472,444 Wafer support device
A wafer support device is provided. The wafer support device includes a plurality of support portions; and a bottom area located among the support portions,...
US-9,472,443 Selectively groundable cover ring for substrate process chambers
Embodiments of a process kit for substrate process chambers are provided herein. In some embodiments, a process kit for a substrate process chamber may include...
US-9,472,442 Wafer processing method
A wafer processing method which includes a first tape attaching step of attaching a first tape to the front side of a wafer and mounting the wafer through the...
US-9,472,441 Substrate processing apparatus
A substrate processing apparatus is used for a spin drying apparatus, a pencil-type scrubbing cleaning apparatus, an IPA drying apparatus and the like, which...
US-9,472,440 Integrated circuit package strip insert assembly
A plurality of inserts adapted are to be received in a plurality of holes in a support plate having a first surface adapted to engage a first surface of an...
US-9,472,439 Reinforcing sheet and method for producing secondary mounted semiconductor device
Provided are a reinforcing sheet which is capable of forming a secondary mounted semiconductor device excellent in impact resistance and which is capable of...
US-9,472,438 Wafer processing laminate, wafer processing member, temporary adhering material for processing wafer, and...
A wafer processing laminate, a wafer processing member, a temporary adhering material for processing wafer, and a method for manufacturing a thin wafer using...
US-9,472,437 Debonding temporarily bonded semiconductor wafers
Described methods and apparatus provide a controlled perturbation to an adhesive bond between a device wafer and a carrier wafer. The controlled perturbation,...
US-9,472,436 Multiple bonding layers for thin-wafer handling
Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is...
US-9,472,435 Tunable temperature controlled substrate support assembly
Implementations described herein provide a substrate support assembly which enables both lateral and azimuthal tuning of the heat transfer between an...
US-9,472,434 Locally heated multi-zone substrate support
Embodiments of the present disclosure provide an electrostatic chuck (ESC) having azimuthal temperature control. In one embodiment, the electrostatic chuck...
US-9,472,433 Mounting port and mounting port opening/closing method
A mounting port that allows an article to be relayed between a worker and a conveying apparatus or a processing device in a clean room includes a shutter that...
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