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Memory cell dynamic grouping using write detection
A memory system and dynamic memory cell programming process thereof is disclosed. The dynamic programming processes comprises the processes of: (a) determining...
Voltage generator, oscillation device and operation method
A voltage generator and an oscillation device, and an operation method thereof are disclosed. The oscillation device includes a non-volatile memory, the voltage...
Non-volatile memory device
According to one embodiment, a non-volatile memory device includes: first memory cell regions including first wirings extending in a first direction, second...
Semiconductor apparatus for reading stored information of a resistor or
A semiconductor apparatus includes a variable resistor, a variable resistor selection unit configured to electrically couple the variable resistor to a sense...
Method of operating memory device using different read conditions
A memory device and a method of operating the memory device are provided for performing a read-retry operation. The method of operating the memory device...
Refresh of nonvolatile memory cells and reference cells with resistance
Resistance drift can be addressed by refreshing the nonvolatile memory cells and reference cells. Different approaches include performing the refresh upon a...
Method and apparatus for decoding memory
A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such...
Resistive switching memory with cell access by analog signal controlled
In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can...
Method of programming a phase change memory and phase change memory device
A method for pre-programming a matrix of phase-change memory cells, including a phase-change material positioned between two conducting electrodes and able to...
Nonvolatile storage reflow detection
A non-volatile storage system includes non-volatile storage elements and one or more managing circuits in communication with the non-volatile storage elements....
Stress balancing of circuits
Methods, systems, and structures for stress balancing field effect transistors subject to bias temperature instability-caused threshold voltage shifts. A method...
SRAM with buffered-read bit cells and its testing
An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a...
Static random access memory
A static random access memory includes a first inverter and a second inverter, a first n-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS...
A semiconductor device may include pad blocks configured for receiving and outputting data. The semiconductor device may also include input/output driving...
Apparatuses and methods for performing logical operations using sensing
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
Semiconductor memory device having sense amplifier
An apparatus includes a memory cell, a bit line coupled to the memory cell, and a sense amplifier configured to amplify a data signal on the bit line read out...
Semiconductor memory device
An object is to increase the retention characteristics of a memory device formed using a semiconductor with a wide bandgap, such as an oxide semiconductor. A...
A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the...
Systems and methods to refresh DRAM based on temperature and based on
A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the...
Semiconductor memory device
A semiconductor memory device may include: a plurality of banks suitable for performing an all bank refresh operation or single bank refresh operation; an...
Semiconductor memory device with dummy memory mat and refresh operating
A semiconductor memory device includes a plurality of normal memory mats, one or more of which includes a redundancy word line, a dummy memory mat suitable for...
Method of operating memory device and method of operating memory system
including the same
A method of operating a memory device comprises receiving a first row address corresponding to a first word line in the first sub bank array and corresponding...
Hybrid magnetoresistive read only memory (MRAM) cache mixing single-ended
and differential sensing
A hybrid cache architecture uses magnetoresistive random-access memory (MRAM) caches but has two different types of bit cell sensing. One type of bit cell...
Magnetic memory having two transistors and two magnetic tunnel junctions
per memory cell
Circuits and methods for driving generating multiple word line voltages used for writing to two-transistor two-magnetic tunnel junction (2T2MTJ) spin-torque...
Semiconductor device including a clock generating circuit for generating
an internal signal having a coarse...
A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an...
Method and apparatus for timing adjustment
A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A...
Semiconductor device including spiral data path
A semiconductor device disclosed in this disclosure includes a first terminal formed above a first surface of a semiconductor substrate, a second terminal...
Apparatuses and methods for improving retention performance of
hierarchical digit lines
Apparatuses and methods for improving retention performance of hierarchical digit lines are disclosed herein. An example apparatus may include a first digit...
Semiconductor device having dummy cell region that are symmetrically
disposed about peripheral region
A semiconductor device includes a plurality of memory cell region regions with each memory cell region region having a plurality of normal memory cell regions,...
Semiconductor device and operating method thereof
A semiconductor device including an input unit suitable for transferring external command signals provided from an external device to an internal device and a...
Techniques for accessing a dynamic random access memory array
Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple...
Method and apparatus for implementing a heterogeneous memory subsystem
An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping...
Memory, semiconductor device including the same, and method for testing
A memory includes a first memory cell, a second memory cell, a latch unit, and a switch unit. The latch unit has a true node and a complement node. The switch...
Method and apparatus for maintaining an accurate I/O calibration cell
An integrated circuit includes an input/output "I/O" cell arranged to drive an output signal and an activity analysis unit arranged to generate an activity...
Sense amplifier and related method
A device includes first and second current mirrors electrically connected to reference and cell current sources of a memory array. A first inverter is...
Apparatus power control
The present disclosure includes apparatuses and methods for apparatus power control. A number of embodiments include determining a power profile for each of a...
Systems and methods for stacked semiconductor memory devices
Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller,...
Hard disk drive enclosure base with feed through flexure design and
A storage base having an interior side and an exterior side is described. The storage drive base includes a slotted aperature, a flexible circuit and a...
Identifying and rerecording only the incomplete units of a program
Each data integrity value, from among a plurality of data integrity values each associated with a separate unit of a program comprising a plurality of units, is...
Video editing method and video editing device
A video editing method for a video editing device is provided. The method includes: obtaining an editing segment of a video, wherein the editing segment follows...
Concurrent transcoding of streaming video for immediate download
Aspects relate to transcoding a video at substantially the same time as the video is streamed so that upon completion of streaming, the transcoded video is...
Systems and methods for linked mobile device content generation
Systems and methods are provided for generating a multi-stream composite video. A first mobile device is linked with a second mobile device so that the first...
Systems and methods for side-track aided data recovery
Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for reducing...
Reel rotation synchronization for updating time-varying filter parameters
Methods, systems, and computer program product embodiments for improving track-follow control in a tape storage system using a time-varying filter, by a...
Bulk data erase utilizing an encryption technique
A system and a computer program product are disclosed for eliminating access to data on removable storage media of a removable storage media cartridge. The...
Hard disk drive spindle motor including a base and a base insert formed
from different materials
An axial field motor and a method of assembling the motor are provided. The hard disk drive includes a spindle motor having a fluid dynamic bearing (FDB) motor...
System and method for write protecting portions of magnetic tape storage
Systems and methods for writing data on a magnetic tape having a plurality of partitions and accessed by a tape drive having an associated tape drive processor...
Dual-sided optical discs with normally oriented and inverted text patterns
Disclosed is an optical disc with a first area to store data for playback and that is reflective or opaque to visible light, and a second area that is...
Optical information recording medium and recording/reproducing device
An optical information recording medium has: a recording layer; a super-resolution functional layer; and a protective layer. Letting n be the refractive index...
Plasmon generator including a main body and a front protrusion
A plasmon generator includes a main body, and a front protrusion protruding from the main body. The front protrusion has a proximal portion which is a boundary...