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Patent # Description
US-9,471,527 Semiconductor device and memory system
A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol...
US-9,471,526 Bridge between two different controllers for transferring data between host and storage device
A system including a controller and a bridge module. The controller is configured to (i) communicate with a host via a first interface, and (ii) communicate...
US-9,471,525 Cable with circuitry for communicating performance information
A cable with circuitry that enables the cable to communicate data in one of at least two different signal modes of operation is presented. In a first signal...
US-9,471,524 System bus transaction queue reallocation
A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a...
US-9,471,523 Serial interface systems and methods having multiple modes of serial communication
An enhanced serial interface system is disclosed. The system includes a master component and a slave component. The master component is configured to operate in...
US-9,471,522 Resource allocation by virtual channel management and bus multiplexing
According to embodiments of the invention, methods, computer system, and apparatus for virtual channel management and bus multiplexing are disclosed. The method...
US-9,471,521 Communication system for interfacing a plurality of transmission circuits with an interconnection network, and...
A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read...
US-9,471,520 Controlling operations according to another system's architecture
An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer...
US-9,471,519 Computer system and a computer device
A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller...
US-9,471,518 Multi-modal memory interface
A multi-modal memory interface that supports each of current-mode and voltage-mode signaling by a memory controller with a memory which includes one or more...
US-9,471,517 Memory system, memory module and method to backup and restore system using command address latency
A memory system having a plurality of memory devices includes a controller for separately accessing the memory devices. The memory system includes a data bus...
US-9,471,516 Techniques for transmitting a command to control a peripheral device through an audio port
Examples are disclosed for transmitting a command to control a peripheral device through an audio port. In some examples, the peripheral device may be coupled...
US-9,471,515 Systems, methods, and apparatus for medical device interface connectivity
Certain examples provide systems, apparatus, and methods for adaptive, dynamic medical device connectivity. In an example, a medical device interface system...
US-9,471,514 Mitigation of cyber attacks by pointer obfuscation
A method for protecting a computer includes identifying a first pointer in a data structure used by a computer program indicating a first memory address to be...
US-9,471,513 Cache structure for a computer system providing support for secure objects
A method that protects a confidentiality and an integrity of information in a secure object from other software on the system, said secure object comprising...
US-9,471,512 Secure memory system with fast wipe feature
A Flash-based storage system, card, and/or module comprises a Flash controller configured to encrypt the data pages of a page stripe by shuffling the data...
US-9,471,511 System and methods for CPU copy protection of a computing device
The present disclosure relates to techniques for system and methods for software-based management of protected data-blocks insertion into the memory cache...
US-9,471,510 System and method for cache monitoring in storage systems
A system and method of cache monitoring in storage systems includes storing storage blocks in a cache memory. Each of the storage blocks is associated with...
US-9,471,509 Managing address-independent page attributes
At least one CPU is configured to run a hypervisor at a first access level and at least one guest operating system at a second access level. At the second...
US-9,471,508 Maintaining command order of address translation cache misses and subsequent hits
A computer-implemented method includes storing commands and maintaining an order of receipt of the commands in a command processing unit. The commands include...
US-9,471,507 System and device for page replacement control between virtual and real memory spaces
A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system...
US-9,471,506 Tiered caching and migration in differing granularities
For data processing in a computing storage environment by a processor device, the environment incorporating at least high-speed and lower-speed caches, and...
US-9,471,505 Efficient multi-threaded journal space reclamation
A method for reclaiming space in a journal is disclosed. In one embodiment, such a method includes identifying a plurality of ranks in a storage system. The...
US-9,471,504 Store forwarding cache
A load request is received to retrieve a piece of data from a location in memory and the load request follows one or more store requests in a set of...
US-9,471,503 Demote instruction for relinquishing cache line ownership
A computer system processor of a multi-processor computer system having a cache subsystem, the computer system having exclusive ownership of a cache line,...
US-9,471,502 Multi-core microprocessor configuration data compression and decompression system
An apparatus has a fuse array, a device programmer, and a plurality of cores. The fuse array is disposed on a die, where the fuse array comprises a plurality of...
US-9,471,501 Hardware apparatuses and methods to control access to a multiple bank data cache
Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to...
US-9,471,500 Bucketized multi-index low-memory data structures
Systems and methods for generating and storing a data structure for maintaining cache supporting compression and cache-wide deduplication, including generating...
US-9,471,499 Metadata management
In one embodiment, a copy relationship is established between a storage location at a first site and a storage location at a second site, in a manner which...
US-9,471,498 Memory card access device, control method thereof, and memory card access system
The present invention discloses a memory card access device, the control method thereof and a memory card access system. Said device comprises: a memory card...
US-9,471,497 Methods for combining access history and sequentiality for intelligent prefetching and devices thereof
A method, non-transitory computer readable medium, and device that prefetchs includes identifying a candidate data block from one of one or more immediate...
US-9,471,496 Demoting tracks from a first cache to a second cache by using a stride number ordering of strides in the second...
Information on strides configured in the second cache includes information indicating a number of valid tracks in the strides, wherein a stride has at least one...
US-9,471,495 Method and apparatus for constructing memory access model
Embodiments of the present invention provide a method and an apparatus for constructing a memory access model, and relate to the field of computers. The method...
US-9,471,494 Method and apparatus for cache line write back operation
An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache...
US-9,471,493 Invalidation of index items for a temporary data store
A data processing apparatus and corresponding method of data processing are provided. The data processing apparatus comprises a temporary data store configured...
US-9,471,492 Scatter/gather capable system coherent cache
In accordance with some embodiments, a scatter/gather memory approach may be enabled that is exposed or backed by system memory and uses conventional tags and...
US-9,471,491 Cache configured to log addresses of high-availability data
A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a...
US-9,471,490 Dynamically controlling cache size to maximize energy efficiency
In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a...
US-9,471,489 Caching method and data storage system capable of prolonging service lifetime of a cache memory
In a caching method implemented by a data storage system, a data word as user data is encoded into a codeword that is then written into an area of a cache...
US-9,471,488 Techniques for improving reliability and performance of partially written memory blocks in modern flash memory...
Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a...
US-9,471,487 Data restoration in electronic device
Restoration data is enabled to be written into a nonvolatile memory according to a simple process without using large capacity of a volatile memory. An SRAM...
US-9,471,486 Reducing disturbances in memory cells
Methods for reducing program disturb in non-volatile memories are described. In some embodiments, a non-volatile storage system may acquire a first set of...
US-9,471,485 Difference L2P method
A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to...
US-9,471,484 Flash memory controller having dual mode pin-out
A memory controller of a data storage device, which communicates with a host, is configurable to have at least two different pinout assignments for interfacing...
US-9,471,483 Electronic apparatus having non-volatile memory and method for controlling the same
Electronic apparatus, comprising: non-volatile memory configured to be written to or read from in memory portions which are erased a sector at a time, each said...
US-9,471,482 Input/output trace sampling
Exemplary methods, apparatuses, and systems include a host computer selecting a first workload of a plurality of workloads running on the host computer to be...
US-9,471,481 Virtual storage address threshold for freemained frames
Address-based thresholds for freemained frames are used to determine retention actions. Based, at least in part, on a comparison of a number of freemained...
US-9,471,480 Data processing apparatus with memory rename table for mapping memory addresses to registers
A data processing apparatus has a memory rename table for storing memory rename entries each identifying a mapping between a memory address of a location in...
US-9,471,479 Method and system for simulating job entry subsystem (JES) operation
A method for simulating a behavior of a spooler (220), comprising: receiving (305) an output file (405) produced by the spooler as a result of the execution of...
US-9,471,478 Test machine management
A computer-implemented method includes creating a test suite, wherein the test suite includes a plurality of test cases for execution on a plurality of test...
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