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Patent # Description
US-9,478,584 Nonvolatile memory device and method for manufacturing the same
A nonvolatile memory device includes an insulating layer, oxygen diffusion prevention layers disposed on the insulating layer, a plurality of contact plugs,...
US-9,478,583 Wearable display having an array of LEDs on a conformable silicon substrate
A conformable electronic device and methods for forming such devices are described. Embodiments of a conformable electronic device may include a silicon...
US-9,478,582 Pixel cell and its method for applying voltage generated in a photosensor to a gate capacitance and alternately...
A pixel cell, and a method of use thereof, the pixel cell including: an output, a photosensor configured to generate a first measuring current in a first...
US-9,478,581 Grids in backside illumination image sensor chips and methods for forming the same
A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor...
US-9,478,580 Grounding system for integrated circuits of particular usefulness for circuits incorporating...
A backside-illuminated photosensor array IC is formed in a thinned circuit wafer. Silicon is removed in at least one substrate-stripped zone where a doped...
US-9,478,579 Stacked chip image sensor with light-sensitive circuit elements on the bottom chip
An example imaging sensor system includes a backside-illuminated CMOS imaging array formed in a first semiconductor layer of a first wafer. The CMOS imaging...
US-9,478,578 Stress release layout and associated methods and devices
An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal...
US-9,478,576 Sealed-sidewall device die, and manufacturing method thereof
A method for fabricating a sealed-sidewall device die may include filling grooves of a deeply-grooved device wafer with a sealant, yielding a sealed grooved...
US-9,478,575 Solid-state image sensor
An image sensor includes a first pixel having a first color filter, a first reflection region which reflects light from the first color filter, and a first...
US-9,478,574 Image sensor pixels with light guides and light shield structures
A front-side illuminated image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode, transistor gate structures,...
US-9,478,573 Solid-state imaging apparatus and method of manufacturing the same
A solid-state imaging apparatus includes: an imaging section having a light-receiving portion for receiving light from an object to image the object; and a...
US-9,478,572 Solid-state imaging device, manufacturing method thereof, and electronic apparatus
A solid-state imaging device includes a plurality of photoelectric conversion portions each provided to correspond to each of a plurality of pixels in a...
US-9,478,571 Buried channel deeply depleted channel transistor
Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a...
US-9,478,570 Vertical gate transistor and pixel structure comprising such a transistor
The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric...
US-9,478,569 Solid-state imaging device and electronic device
The present invention relates to a solid-state imaging device. In a pixel array section in the solid-state imaging device, a vertical signal line is provided...
US-9,478,568 Photoelectric conversion device having two switch elements
A photoelectric conversion device includes a first output line, a second output line; and a photoelectric conversion cell. The photoelectric conversion cell...
US-9,478,567 Thin-film transistor, array substrate and display apparatus
A thin-film transistor (TFT) array substrate is provided. The thin-film transistor (TFT) array substrate comprises a substrate having at least a display region;...
US-9,478,566 Array substrate, LCD device and driving method
In an embodiments of the present invention, since two pixel electrodes are arranged in the pixel unit and each of the pixel electrodes is respectively...
US-9,478,565 Array substrate and method for fabricating the same, and display panel
The embodiments of the present invention provide an array substrate, a method for fabricating the array substrate and a display panel. The array substrate...
US-9,478,564 Semiconductor device
An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current....
US-9,478,563 Display device including transistor and manufacturing method thereof
An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display...
US-9,478,562 Array substrate and manufacturing method thereof, display device, thin film transistor and manufacturing method...
An array substrate and manufacturing method thereof, a display device, a thin film transistor and manufacturing method thereof are provided. The manufacturing...
US-9,478,561 Semiconductor memory device and method of fabricating the same
A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A...
US-9,478,560 Memory device
Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the...
US-9,478,559 Semiconductor device and method of fabricating the same
A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes: a memory cell structure formed over a...
US-9,478,558 Semiconductor structure with concave blocking dielectric sidewall and method of making thereof by isotropically...
A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A spacer...
US-9,478,557 Process for 3D NAND memory with socketed floating gate cells
A 3D NAND memory has vertical NAND strings across multiple memory layers above a substrate, with each memory cell of a NAND string residing in a different...
US-9,478,556 Semiconductor memory device
A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a...
US-9,478,555 Method for processing a carrier, a carrier, and a split gate field effect transistor structure
According to various embodiments, a method for processing a carrier may include: doping a carrier with fluorine such that a first surface region of the carrier...
US-9,478,554 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are...
US-9,478,553 SRAM cell connection structure
A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a second pull-up transistor, and a first pull-down transistor and a second...
US-9,478,552 Static random access memory and manufacturing method thereof
A static random access memory and the manufacturing method thereof are provided. By forming the specific gate structure(s) to be concave gate structure(s) and...
US-9,478,551 Semiconductor devices and methods of manufacturing the same
A semiconductor device includes a channel layer over an active region, first and second field regions adjacent the active region, and a gate structure over the...
US-9,478,550 Arrays of vertically-oriented transistors, and memory arrays including vertically-oriented transistors
An array includes vertically-oriented transistors. The array includes rows of access lines and columns of data/sense lines. Individual of the rows include an...
US-9,478,549 FinFET with dielectric isolation by silicon-on-nothing and method of fabrication
An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of...
US-9,478,548 Semiconductor devices and methods of manufacturing semiconductor devices
A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact...
US-9,478,547 Semiconductor device and method of manufacturing the same
Dishing of a plate of a capacitor is suppressed in a structure where the top of the plate is flush with a top of an interconnection. Double interlayer...
US-9,478,546 LC module layout arrangement for contact opening etch windows
A lay-out arrangement for LC modules in 3D semiconductor memories is described that avoids large step height. The arrangement creates insulating/conducting...
US-9,478,545 Method for manufacturing semiconductor device and semiconductor device
A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate. A first insulating film is around the first and second...
US-9,478,544 Method for forming a germanium channel layer for an NMOS transistor device, NMOS transistor device and CMOS device
The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to a transistor device comprising a...
US-9,478,543 Semiconductor integrated circuit
A low side control circuit and a high side control circuit are disposed in first and second n type well regions, respectively. A third n.sup.- type well region...
US-9,478,542 Multi-gate device with planar channel
A semiconductor device includes a substrate having a well region implanted with a first dopant by a first well implantation and a non-doped section blocked from...
US-9,478,541 Half node scaling for vertical structures
A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes...
US-9,478,540 Adaptive fin design for FinFETs
A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are...
US-9,478,539 Compound semiconductor device and method of manufacturing the same
An AlGaN/GaN HEMT includes a compound semiconductor stack structure; an element isolation structure which demarcates an element region on the compound...
US-9,478,538 Methods for forming transistor devices with different threshold voltages and the resulting devices
A method includes forming first and second gate cavities so as to expose first and second portions of a semiconductor material. A gate insulation layer is...
US-9,478,537 High-gain wide bandgap darlington transistors and related methods of fabrication
A packaged power electronic device includes a wide bandgap bipolar driver transistor having a base, a collector, and an emitter terminal, and a wide bandgap...
US-9,478,536 Semiconductor device including fin capacitors
A semiconductor device with fin capacitors is disclosed. The device includes a substrate including a first region and a second region; first and second active...
US-9,478,535 Semiconductor device comprising oxide semiconductor film
A semiconductor device including a capacitor having an increased charge capacity without decreasing an aperture ratio is provided. The semiconductor device...
US-9,478,534 Lateral BiCMOS replacement metal gate
A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first...
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