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Method and apparatus for forming an integrated circuit with a metalized
resistor in a standard cell configuration
An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate...
Electro static discharge protection circuit and electronic device having
An electro static discharge (ESD) protection circuit including a signal transmission line coupled to an external input terminal, the ESD protection circuit...
Semiconductor device comprising an ESD protection device, an ESD
protection circuitry, an integrated circuit...
A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD...
Semiconductor device and manufacturing method of the same
A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic...
Electrostatic discharge protection system
An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad...
Devices, systems and methods using through silicon optical interconnects
Some implementations provide a semiconductor device that includes a first die and an optical receiver. The first die includes a back side layer having a...
Semiconductor light emitting device
A light emitting device includes a substrate, a light emitting element mounted on the substrate, a light transmissive member placed on an upper surface of the...
Light emitting module
Disclosed herein is a light emitting module. The light emitting module according to an exemplary embodiment includes a circuit board having a cavity and...
One semiconductor device includes nine surface micro-bumps laid out in a 3.times.3 matrix on a semiconductor substrate, a transistor that contains first and...
Multi-die semiconductor structure with intermediate vertical side chip and
semiconductor package for same
Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an...
Semiconductor packages and methods of fabricating the same
A semiconductor package including a lower package and an upper package provided may be provided. The lower package includes a lower package substrate, a lower...
Electronic part, electronic device, and manufacturing method
An electronic part includes: a substrate; a first electrode configured to extend through the substrate and have a first opening size; a second electrode...
A device comprises a top package mounted on a bottom package through a joint structure, wherein the joint structure comprises a solder ball of the top package...
Solid-state imaging device, imaging apparatus, substrate, semiconductor
device and method of manufacturing the...
A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a...
Package including a semiconductor die and a capacitive component
In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar...
Method for permanent connection of two metal surfaces
A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of...
Electronic device package structure and method of fabricating the same
In one embodiment, an electronic device package structure includes an electronic die having conductive pads on one surface. The one surface is further attached...
Methods of operating bonding machines for bonding semiconductor elements,
and bonding machines
A method of operating a bonding machine for bonding semiconductor elements is provided. The method includes the steps of: (a) measuring a time based z-axis...
Semiconductor packages including interconnection members
A semiconductor package may include a main substrate, a sub-substrate spaced apart from the main substrate by a gap, and a semiconductor chip disposed on the...
Pre-package and methods of manufacturing semiconductor package and
electronic device using the same
Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a...
Semiconductor device with conductive pillars having recesses or
protrusions to detect interconnect continuity...
A semiconductor device has a semiconductor die and conductive pillar with a recess or protrusion formed over a surface of the semiconductor die. The conductive...
Semiconductor packaging structure having stacked seed layers
A semiconductor packaging structure includes a chip, a metal barrier layer, a dielectric layer and two metal seed layers. The chip has a top surface, connection...
Methods and apparatus of packaging semiconductor devices
Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise...
Self-aligned under bump metal
An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with...
Mechanically anchored backside C4 pad
The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored...
Microwave integrated circuit (MMIC) damascene electrical interconnect for
microwave energy transmission
A semiconductor structure having a semiconductor layer having an active device therein. A dielectric structure is disposed over the semiconductor layer, such...
Integrated circuit assembly with faraday cage
An integrated circuit assembly is formed with an insulating layer, a semiconductor layer, an active device, first, second, and third electrically conductive...
Multilayer pattern transfer for chemical guides
Approaches for multilayer pattern transfer for chemical guides are provided. In a typical embodiment, a device is formed by forming an etch mask layer (e.g., a...
Guard ring design structure for semiconductor devices
A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells...
Microelectronic assemblies with cavities, and methods of fabrication
Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the...
An integrated device with high insulation tolerance is provided. A groove having an inclined side surface is provided between adjacent devices. When a side...
Device identification assignment and total device number detection
Various embodiments comprise apparatuses to assign a respective one of a sequence of unique device identification (ID) values to each die in a stacked device....
Substrate processing and alignment
A substrate can efficiently be manufactured by separating the alignment and the actual processing when an alignment mark is provided, which is fixed with...
Interposer substrate, semiconductor structure and fabricating process
Described herein are interposer substrate designs for warpage control, semiconductor structures including said interposer substrates, and fabricating processes...
Semiconductor package structure and method for manufacturing the same
A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure has a substrate and a die stack of n...
Through package via (TPV)
A through package vias (TPV), a package including a plurality of the TPVs, and a method of forming the through package via are provided. Embodiments of a...
Single spacer process for multiplying pitch by a factor greater than two
and related intermediate IC structures
Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n.gtoreq.2, tiers of stacked mandrels are...
Wafer to wafer structure and method of fabricating the same
A wafer to wafer structure includes a first wafer, a second wafer. A first bonding layer and a second bonding layer are disposed between the first wafer and the...
Three dimensional memory device containing aluminum source contact via
structure and method of making thereof
A low-stress contact via structure for a device employing an alternating stack of insulating layers and electrically conductive layers over a substrate can be...
Digital data device interconnects
Digital data system disposed on a substrate includes a digital data device and at least one digital data interconnect disposed on the substrate. The digital...
Semiconductor device and a method increasing a resistance value of an
A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions...
Integrated circuit having slot via and method of forming the same
An integrated circuit includes a first conductive line on a first metal level of the integrated circuit. The integrated circuit further includes a second...
Integrated circuit package substrate with openings surrounding a
Integrated circuit packages with openings surrounding a conductive via on a substrate layer are disclosed. An integrated circuit package may include a substrate...
Capacitor from second level middle-of-line layer in combination with
A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active...
Semiconductor dies with reduced area consumption
The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on...
Reducing loadline impedance in a system
In one embodiment, the present invention includes a semiconductor device mounted to a first side of a circuit board; and at least one voltage regulator device...
A semiconductor package includes a substrate including connection pads, a first semiconductor, and conductive wires. The first semiconductor chip is stacked on...
Semiconductor device and method of forming topside and bottom-side
interconnect structures around core die with TSV
A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked...
Semiconductor device and method of stacking semiconductor die on a fan-out
A semiconductor device has a first semiconductor die. A first interconnect structure, such as a conductive pillar including a bump formed over the conductive...
Semiconductor packages and methods of formation thereof
In accordance with an embodiment of the present invention, a semiconductor device includes a lead frame having a die paddle and a lead. A chip is disposed over...