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| Patent # | Description |
|---|---|
| US-9,478,483 |
Semiconductor device having a chip mounting portion on which a separated
plated layer is disposed The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second... |
| US-9,478,482 |
Offset integrated circuit packaging interconnects One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, and a plurality of solder... |
| US-9,478,481 |
Semiconductor device, method for manufacturing same, and electronic
component An electrode layer is formed on a gate insulating film. An interlayer insulating film is formed on the gate insulating firm. A lower pad is formed by a... |
| US-9,478,480 |
Alignment mark and method of formation In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate... |
| US-9,478,479 |
Thermal management system and method A thermal management system is provided. The thermal management system includes at least one heat sink including one or more respective fins, wherein the one or... |
| US-9,478,478 |
Electronic device assemblies and vehicles employing dual phase change
materials Electronic device assemblies employing dual phase change materials and vehicles incorporating the same are disclosed. In one embodiment, an electronic device... |
| US-9,478,477 |
Semiconductor device A semiconductor device includes a semiconductor element having a semiconductor chip and connection terminals, a cooling fin to which the semiconductor element... |
| US-9,478,476 |
Package for a microelectronic die, microelectronic assembly containing
same, microelectronic system, and method... A package for a microelectronic die (110) includes a first substrate (120) adjacent to a first surface (112) of the die, a second substrate (130) adjacent to... |
| US-9,478,475 |
Apparatus and package structure of optical chip An apparatus includes a package structure. The package structure includes a chip, a conductive structure over the chip, a molding structure surrounding and... |
| US-9,478,474 |
Methods and apparatus for forming package-on-packages Methods and apparatus are disclosed for a package or a package-on-package (PoP) device. An IC package or a PoP device may comprise an electrical path connecting... |
| US-9,478,473 |
Fabricating a microelectronics lid using sol-gel processing A method for fabrication of a lid for a microelectronic device is described, wherein the microelectronic device comprises of a die and a laminate. A gel is... |
| US-9,478,472 |
Substrate components for packaging IC chips and electronic device packages
of the same Substrate components for packaging IC chips and electronic device packages are disclosed. A substrate component for packaging IC chips comprises: a glass core... |
| US-9,478,471 |
Apparatus and method for verification of bonding alignment Presented herein is a device comprising a common node disposed in a first wafer' a test node disposed in a first wafer and having a plurality of test pads... |
| US-9,478,470 |
System for electrical testing of through-silicon vias (TSVs), and
corresponding manufacturing process An embodiment of a process for manufacturing a system for electrical testing of a through via extending in a vertical direction through a substrate of... |
| US-9,478,469 |
Integrated circuit comprising buffer chain Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a... |
| US-9,478,468 |
Dual metal contact scheme for CMOS devices A semiconductor structure includes non-metal semiconductor alloy containing contact structures for an n-type field effect transistor (nFET) and a metal... |
| US-9,478,467 |
Semiconductor device including power and logic devices and related
fabrication methods Semiconductor device structures and related fabrication methods are provided. An exemplary fabrication method involves forming a layer of gate electrode... |
| US-9,478,466 |
Metal gate structure and method A method comprises removing a dummy gate electrode layer to form a gate trench in a dielectric layer over a substrate, forming a resistor trench over the... |
| US-9,478,465 |
Wafer processing method A method of processing a wafer having a device area where a plurality of devices are formed and a peripheral marginal area surrounding the device area on the... |
| US-9,478,464 |
Method for manufacturing through-hole silicon via A method for manufacturing a through-hole silicon via (TSV) employs the conventional trench insulation process to readily manufacture a through-hole silicon via... |
| US-9,478,463 |
Device and method for improving RF performance A semiconductor device and method of fabricating the semiconductor device are provided. The semiconductor device includes a first substrate including a... |
| US-9,478,462 |
SAV using selective SAQP/SADP Methods of forming a SAV using a selective SAQP or SADP process are provided. Embodiments include providing on a TiN layer and dielectric layers alternating... |
| US-9,478,461 |
Conductive line structure with openings Wide and narrow mandrels that are used to form sidewall spacers for patterning are formed in a sacrificial layer with openings in wide mandrels near sides of... |
| US-9,478,460 |
Cobalt selectivity improvement in selective cobalt process sequence Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. Embodiments described... |
| US-9,478,459 |
Device and methods for small trench patterning A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures, and an etch buffer layer. The... |
| US-9,478,458 |
Waveguide and semiconductor packaging A method and apparatus for integrating individual III-V MMICs into a micromachined waveguide package is disclosed. MMICs are screened prior to integration,... |
| US-9,478,457 |
Shallow trench isolation structures in semiconductor device and method for
manufacturing the same Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is... |
| US-9,478,456 |
Semiconductor device with composite drift region A device includes a semiconductor substrate, a channel region in the semiconductor substrate having a first conductivity type, and a composite drift region in... |
| US-9,478,455 |
Thermal pyrolytic graphite shadow ring assembly for heat dissipation in
plasma chamber Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a shadow ring... |
| US-9,478,454 |
Dicing tape-integrated film for semiconductor back surface The present invention provides a dicing tape-integrated film for semiconductor back surface, including a film for flip chip type semiconductor back surface for... |
| US-9,478,453 |
Sacrificial carrier dicing of semiconductor wafers Mechanisms are provided for sacrificial carrier dicing of semiconductor wafers. A bottom layer of a semiconductor wafer is bonded to a top layer of a... |
| US-9,478,452 |
Small production device and production system using the same A production system to facilitate the commonization of front chambers among a plurality of production devices that are different in the kind of a process to be... |
| US-9,478,451 |
Robot having interchangeability features An apparatus including a stator configured to be stationarily connected to a housing; and a rotor configured to have a robot arm connected thereto. The rotor... |
| US-9,478,450 |
Wafer shipper A wafer container for holding a spaced stack of thin wafers, comprising an H-bar carrier, a base portion for receiving same, a base wafer cushion attached at... |
| US-9,478,449 |
Floating substrate monitoring and control device, and method for the same Disclosed is a process tunnel (102) through which substrates (140) may be transported in a floating condition between two gas bearings (124, 134). To monitor... |
| US-9,478,448 |
Thermal treatment system and method of performing thermal treatment and
method of manufacturing CIGS solar cell... Disclosed is a thermal treatment system which enables a uniform temperature distribution and a uniform concentration distribution of reaction gas in an entire... |
| US-9,478,447 |
Substrate support with wire mesh plasma containment Embodiments of substrate supports having a wire mesh plasma containment are provided herein. In some embodiments, a substrate support may include a plate... |
| US-9,478,446 |
Load lock chamber A semiconductor processing tool is disclosed, the tool having a frame forming at least one chamber with an opening and having a sealing surface around a... |
| US-9,478,445 |
Substrate liquid processing apparatus and method for detecting abnormality
of air flow A substrate liquid processing apparatus includes a substrate holding unit configured to hold and rotate a substrate; a processing liquid nozzle configured to... |
| US-9,478,444 |
Mechanisms for cleaning wafer and scrubber Embodiments of mechanisms for cleaning a wafer are provided. A method for cleaning a wafer includes cleaning a wafer by using a wafer scrubber and cleaning the... |
| US-9,478,443 |
Semiconductor package and method of forming the same According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a chip having a plurality of joint pads; a... |
| US-9,478,442 |
Reduced-noise reference voltage platform for a voltage converter device An electronic system, a reduced-noise reference voltage platform for a voltage converter device, and a method of manufacture of a reduced-noise reference... |
| US-9,478,441 |
Method for forming a superjunction device with improved ruggedness An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge... |
| US-9,478,440 |
Low-pressure chemical vapor deposition apparatus and thin-film deposition
method thereof A low-pressure chemical vapor deposition (LPCVD) apparatus and a thin-film deposition method thereof. The apparatus comprises a reaction furnace, having... |
| US-9,478,439 |
Substrate etching method Embodiments of the invention provide a substrate etching method, which includes: a deposition operation for depositing a polymer on a side wall of a silicon... |
| US-9,478,438 |
Method and apparatus to deposit pure titanium thin film at low temperature
using titanium tetraiodide precursor Methods of depositing highly conformal and pure titanium films at low temperatures are provided. Methods involve exposing a substrate to titanium tetraiodide,... |
| US-9,478,437 |
Methods for repairing low-k dielectrics using carbon plasma immersion Methods for repairing low-k dielectrics using a plasma immersion carbon doping process are provided herein. In some embodiments, a method of repairing a low-k... |
| US-9,478,436 |
Methods for forming patterns in honeycomb array A method for forming patterns includes forming ellipse pillars on an underlying layer. The ellipse pillar has an elongated feature and includes nose sides and... |
| US-9,478,435 |
Method for directed self-assembly and pattern curing Techniques disclosed herein include methods for DSA patterning and curing of DSA patterns. Techniques include curing phase-separated block copolymers using... |
| US-9,478,434 |
Chlorine-based hardmask removal A method of removing titanium nitride hardmask is described. The hardmask resides above a low-k dielectric layer prior to removal and the low-k dielectric layer... |
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