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Patent # Description
US-9,477,624 Controlling bus access in a real-time computer system
In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from...
US-9,477,623 Barrier transactions in interconnects
Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry...
US-9,477,622 Deterministic method to support multiple producers with multiple consumers in peer or hierarchical systems
A transaction processing method is disclosed to solve the issue of multiple producers (software and hardware) and one or more consumers operating in a peer or...
US-9,477,621 Bandwidth control method for an on-chip system
The invention concerns a bandwidth control method in an on-chip system comprising at least one main master module, at least one secondary master module, at...
US-9,477,620 Storage system for changing a data transfer speed and a method of changing the data transfer speed thereof
A storage device of a storage system includes a device Direct Memory Access (DMA) configured to calculate a data transfer amount based on size information of...
US-9,477,619 Programmable latency count to achieve higher memory bandwidth
Disclosed herein are system, method and/or computer program product embodiments for increasing memory bandwidth when accessing a plurality of memory devices. An...
US-9,477,618 Information processing device, information processing system, storage medium storing program for controlling...
An information processing device, comprising: a memory; and one or more central processing units coupled to the memory and configured to: control accesses to a...
US-9,477,617 Memory buffering system that improves read/write performance and provides low latency for mobile systems
A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host...
US-9,477,616 Devices, systems, and methods of reducing chip select
Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a...
US-9,477,615 Bi-directional low latency bus mode
A method for low latency data transfers between a wireless root device and a wireless endpoint device connected through a wireless peripheral-interconnect bus....
US-9,477,614 Sector map-based rapid data encryption policy compliance
To comply with a policy for a computing device indicating that data written by the computing device to the storage volume after activation of the policy be...
US-9,477,613 Position-based replacement policy for address synonym management in shared caches
A computer-implemented method includes receiving a request to access a cache entry in a shared cache. The request references a synonym for the cache entry. A...
US-9,477,612 Memory system for reliable predicted sequential read operation
A memory system includes a plurality of memory chips each including memory regions and page buffers; an address table suitable for storing mapping information...
US-9,477,611 Final level cache system and corresponding methods
A data access system including a processor and a final level cache module. The processor is configured to generate a request to access a first physical address....
US-9,477,610 Address range priority mechanism
Method and apparatus to efficiently manage data in caches. Data in caches may be managed based on priorities assigned to the data. Data may be requested by a...
US-9,477,609 Enhanced transactional cache with bulk operation
Described herein is a technology for providing enhanced transactional caching. In accordance with one aspect, a transactional cache associated with a database...
US-9,477,608 Apparatus and method for rapid fuse bank access in a multi-core processor
An apparatus includes a fuse array, a random access memory (RAM), and a plurality of cores. The fuse array is disposed on a die, where the fuse array has a...
US-9,477,607 Adaptive record caching for solid state disks
A storage controller receives a request that corresponds to an access of a track. A determination is made as to whether the track corresponds to data stored in...
US-9,477,606 Adaptive record caching for solid state disks
A storage controller receives a request that corresponds to an access of a track. A determination is made as to whether the track corresponds to data stored in...
US-9,477,605 Memory hierarchy using row-based compression
A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The...
US-9,477,604 Caching of look-up rules based on flow heuristics to enable high speed look-up
In one embodiment, a computer program product includes a computer readable storage medium having computer readable program code embodied therewith, the computer...
US-9,477,603 System and method for partitioning of memory units into non-conflicting sets
A system and method of operation exploit the limited associativity of a single cache set to force observable cache evictions and discover conflicts. Loads are...
US-9,477,602 Cache refill control
A method and a device are disclosed for a cache memory refill control.
US-9,477,601 Apparatus and method for determining a sector division ratio of a shared cache memory
An apparatus includes a shared cache memory and a controller. The shared cache memory is configured to be divided into sectors by assigning one or more ways to...
US-9,477,600 Apparatus and method for shared cache control including cache lines selectively operable in inclusive or...
A data processing system 2 includes a cache hierarchy having a plurality of local cache memories and a shared cache memory 18. State data 30, 32 stored within...
US-9,477,599 Write combining cache microarchitecture for synchronization events
A method, computer program product, and system is described that enforces a release consistency with special accesses sequentially consistent (RCsc) memory...
US-9,477,598 System and method for implementing cache consistent regional clusters
When multiple regional data clusters are used to store data in a system, maintaining cache consistency across different regions is important for providing a...
US-9,477,597 Techniques for different memory depths on different partitions
Embodiments of the present technology are directed toward techniques for enabling different memory partitions to have different memory depths.
US-9,477,596 LBA bitmap usage
Systems and methods are disclosed for logical block address ("LBA) bitmap usage for a system having non-volatile memory ("NVM"). A bitmap can be stored in...
US-9,477,595 Managing the write performance of an asymmetric memory system
Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The...
US-9,477,594 Semiconductor device and control method for reading instructions
A system-in-package semiconductor device with a CPU, a first flash memory configured to store first instructions to be executed by the CPU, and a second flash...
US-9,477,593 Semiconductor device and operating method thereof
A semiconductor device remaps the relationship between logical addresses and physical addresses of a semiconductor memory device at each first interval. The...
US-9,477,592 Localized fast bulk storage in a multi-node computer system
A high performance computing (HPC) system includes computing blades having a first region that includes computing circuit boards having processors for...
US-9,477,591 Memory access requests in hybrid memory system
Incoming memory access requests are routed in a set of incoming queues, the incoming memory access requests comprise a range of host logical block addresses...
US-9,477,590 Weave sequence counter for non-volatile memory systems
Systems and methods are disclosed for providing a weave sequence counter ("WSC") for non-volatile memory ("NVM") systems. The WSC can identify the sequence in...
US-9,477,589 Storage device that performs a de-duplication operation, and method of operating the same
A storage device is provided which includes a nonvolatile memory device configured to store a plurality of reference data, a memory configured to store a hash...
US-9,477,588 Method and apparatus for allocating memory for immutable data on a computing device
A system that allocates memory for immutable data on a computing device. The system allocates a memory region on the computing device to store immutable data...
US-9,477,587 Method and apparatus for a volume management system in a non-volatile memory device
Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks...
US-9,477,586 Power-aware memory controller circuitry
Memory controller circuitry may process the memory access requests by reordering the sequence of requests. Reordering the sequence of requests may decrease the...
US-9,477,585 Real time analysis and control for a multiprocessor system
System and method for testing a device under test (DUT) that includes a multiprocessor array (MPA) executing application software at operational speed. The...
US-9,477,584 System and method to test executable instructions
This document discusses, among other things, a method of testing an Application Programming Interface (API) call that includes receiving data identifying a...
US-9,477,583 Automating functionality test cases
A computer implemented method and system including techniques for developing and executing automated test cases are described herein. In one embodiment, a test...
US-9,477,582 Executable software specification generation
Executable software specification generation can include recording interactions with a user-interface (UI) mockup for a particular program and generating a...
US-9,477,581 Integrated system and method for validating the functionality and performance of software applications
The system and method presented provides a multi-phase, end-to-end integrated process for testing application software using a standard software testing tool....
US-9,477,580 System and method for determining test coverage
A computer-implemented method, computer program product, and system is provided for determining test coverage. In an implementation, a method may include...
US-9,477,579 Embedded software debug system with partial hardware acceleration
An embedded software debug system with partial hardware acceleration includes a computer that executes a debug software stack. The debug software stack includes...
US-9,477,578 Sequence-program-debugging supporting apparatus
A sequence-program-debugging supporting apparatus includes a configuration editing unit that receives a disabling unit from a PLC, a variable retaining unit...
US-9,477,577 Method and apparatus for enabling an executed control flow path through computer program code to be determined
A method of enabling an executed control flow path through computer program code to be determined. The method comprising modelling cumulative instruction counts...
US-9,477,576 Using application state data and additional code to resolve deadlocks
A computer captures a thread state data of a first program. The computer generates a second program by applying a first program patch to the first program. The...
US-9,477,575 Method and system for implementing a multi-threaded API stream replay
A method for debugging and includes receiving a request for capturing a frame generated by a graphics application implementing application threads executing...
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