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Patent # Description
US-9,484,476 Photoelectric conversion device
It is an object of the present invention to improve photoelectric conversion efficiency in a photoelectric conversion device. The photoelectric conversion...
US-9,484,475 Semiconductor ferroelectric compositions and their use in photovoltaic devices
Disclosed herein are ferroelectric perovskites characterized as having a band gap, Egap, of less than 2.5 eV. Also disclosed are compounds comprising a solid...
US-9,484,474 Ultrananocrystalline diamond contacts for electronic devices
A method of forming electrical contacts on a diamond substrate comprises producing a plasma ball using a microwave plasma source in the presence of a mixture of...
US-9,484,473 Anti-reflection glass substrate
A glass substrate of which at least one surface multiple concave and convex portions. Rp representing the size of the convex portion is 37 nm to 200 nm; a tilt...
US-9,484,472 Semiconductor device, electrical device system, and method of producing semiconductor device
A semiconductor device includes a first semiconductor layer having a first conductive type; a circuit layer including a second semiconductor layer; and a...
US-9,484,471 Compound varactor
Embodiments include apparatuses and methods related to a compound varactor. A first varactor in the compound varactor may include a collector layer and a first...
US-9,484,470 Method of fabricating a GaN P-i-N diode using implantation
A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor...
US-9,484,469 Thin film device with protective layer
Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal...
US-9,484,468 Thin film transistor and manufacturing method thereof, array substrate, and display apparatus
The present invention provides a thin film transistor and a manufacturing method thereof, an array substrate, and a display apparatus. The thin film transistor...
US-9,484,467 Semiconductor device
A semiconductor device with significantly low off-state current is provided. An oxide semiconductor material in which holes have a larger effective mass than...
US-9,484,466 Thin film transistor
A thin film transistor includes: a gate electrode; a source electrode; a drain electrode facing the source electrode; an oxide semiconductor layer disposed...
US-9,484,465 Array substrate, manufacturing method thereof and display device
A array substrate is disclosed. The array substrate includes: a substrate (10); and a first gate metal layer (111), a first gate insulating layer (121), a...
US-9,484,464 Structure and method for adjusting threshold voltage of the array of transistors
A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed....
US-9,484,463 Fabrication process for mitigating external resistance of a multigate device
A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material,...
US-9,484,462 Fin structure of fin field effect transistor
An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the...
US-9,484,461 Integrated circuit structure with substrate isolation and un-doped channel
The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure formed on a substrate; a gate stack formed over...
US-9,484,460 Semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode...
A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The...
US-9,484,459 Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the...
A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the...
US-9,484,458 Semiconductor device including first and second trenches having substantially equal depths
A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in...
US-9,484,457 Vertical floating body storage transistors formed in bulk devices and having buried sense and word lines
A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture....
US-9,484,456 Semiconductor device and manufacturing method of the same
A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer....
US-9,484,455 Isolation NLDMOS device and a manufacturing method therefor
An isolation NLDMOS device including: an N well and a P well adjacent to each other on an upper part of a P substrate; on the upper part of the P well are...
US-9,484,454 Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate "bump" structure
A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field "bump" oxide region and an optional raised dielectric structure that...
US-9,484,453 Device structure and methods of making high density MOSFETs for load switch and DC-DC applications
Aspects of the present disclosure describe a high density trench-based power. The active devices may have a two-step gate oxide. A lower portion may have a...
US-9,484,452 Integrating enhancement mode depleted accumulation/inversion channel devices with MOSFETs
A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are...
US-9,484,451 MOSFET active area and edge termination area charge balance
A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at...
US-9,484,450 Integrated channel diode
A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over...
US-9,484,449 Integrated circuits with diffusion barrier layers and processes for preparing integrated circuits including...
Integrated circuits with a diffusion barrier layers, and processes for preparing integrated circuits including diffusion barrier layers are provided herein. An...
US-9,484,448 Semiconductor gas sensor and method for producing the same
A technique capable of realizing a semiconductor gas sensor having a high rising response speed is provided. A gate insulating film (e.g., a SiO.sub.2 film) is...
US-9,484,447 Integration methods to fabricate internal spacers for nanowire devices
A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device...
US-9,484,446 Semiconductor device and method for manufacturing the same
A semiconductor device includes: a nitride semiconductor layer; a first silicon nitride film that is formed on the nitride semiconductor layer, has a first...
US-9,484,445 Semiconductor device and semiconductor device manufacturing method
An n-type low lifetime adjustment region is provided in a portion inside an n.sup.- type drift region deeper than the bottom surface of a termination p-type...
US-9,484,444 Semiconductor device with a resistance element in a trench
A semiconductor device has a semiconductor substrate, an insulating film, a semiconductor element and a resistance element. The semiconductor substrate has a...
US-9,484,443 Semiconductor device
A semiconductor device includes a semiconductor layer opposing to a bottom surface and a side surface of a gate electrode. An insulation film is provided...
US-9,484,442 Method of fabricating thin-film transistor substrate
A method of fabricating a TFT substrate in which a thin-film transistor is formed on a substrate, includes: forming an oxide semiconductor layer above the...
US-9,484,441 Method for fabricating transistor having hard-mask layer
A method for fabricating a transistor including the following steps is provided. First, a gate electrode is formed on a substrate, and a gate insulating layer...
US-9,484,440 Methods for forming FinFETs with non-merged epitaxial fin extensions
Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a...
US-9,484,439 III-V fin on insulator
A method of forming a semiconductor structure in which a III-V compound semiconductor channel fin portion is formed on a dielectric material is provided. The...
US-9,484,438 Method to improve reliability of replacement gate device
A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k...
US-9,484,437 Lateral double diffused metal oxide semiconductor device and manufacturing method thereof
The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device...
US-9,484,436 Power LDMOS semiconductor device with reduced on-resistance and manufacturing method thereof
An electronic semiconductor device including a semiconductor body having a first structural region and a second structural region, which extends on the first...
US-9,484,435 MOS transistor with varying channel width
One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the...
US-9,484,434 Inducement of strain in a semiconductor layer
Strain is induced in a semiconductor layer. Embodiments include inducing strain by, for example, creation of free surfaces.
US-9,484,433 Method of manufacturing a MISFET on an SOI substrate
Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure...
US-9,484,432 Contact resistance reduction employing germanium overlayer pre-contact metalization
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be...
US-9,484,431 Pure boron for silicide contact
A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench...
US-9,484,430 Back-end transistors with highly doped low-temperature contacts
A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer...
US-9,484,429 High electron mobility transistor (HEMT) capable of absorbing a stored hole more efficiently and method for...
A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first electrode, a second electrode, a...
US-9,484,428 Non-planar exciton transistor (BiSFET) and methods for making
A semiconductor device includes a first gate electrode defined on a base layer. A first plurality of layers is disposed on a first sidewall of the first gate...
US-9,484,427 Field effect transistors having multiple effective work functions
Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect...
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