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Patent # Description
US-9,484,325 Interconnections for a substrate associated with a backside reveal
An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An...
US-9,484,324 Method of manufacturing semiconductor device
A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a...
US-9,484,323 Method of manufacturing a semiconductor package and wire bonding apparatus for performing the same
In a method of manufacturing a semiconductor package, a first semiconductor chip is adhered to a package substrate. An end portion of a wire is bonded to a...
US-9,484,322 Semiconductor packages with sliding interconnect structure
A semiconductor package includes a first substrate including a plurality of first connecting portions disposed thereon, a second substrate disposed on a portion...
US-9,484,321 High frequency device
A high frequency device includes a base plate having a main surface, a dielectric on the main surface, along a first side of the base plate, a signal line on...
US-9,484,320 Vertically packaged integrated circuit
A device comprises a semiconductor package including a first integrated circuit (IC) die including a plurality of through silicon vias (TSVs). The TSVs are...
US-9,484,319 Semiconductor device and method of forming extended semiconductor device with fan-out interconnect structure to...
A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. Contact pads are formed on a surface of the semiconductor die. The...
US-9,484,318 Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding...
US-9,484,317 Scheme for connector site spacing and resulting structures
A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the...
US-9,484,316 Semiconductor devices and methods of forming thereof
In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major...
US-9,484,315 Chip structure having bonding wire
A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of...
US-9,484,314 Word line hook up with protected air gap
A method of forming a semiconductor device includes forming a plurality of word lines separated by air gaps with contact pad structures connected to the word...
US-9,484,313 Semiconductor packages with thermal-enhanced conformal shielding and related methods
The semiconductor package includes a substrate, a die, a first metal layer, a second metal layer and an optional seed layer. The package body at least partially...
US-9,484,312 Inductor shielding structure, integrated circuit including the same and method of forming the integrated circuit
An inductor shielding structure includes a first conductive layer including a plurality of first conductive lines having a first width and a plurality of second...
US-9,484,311 Chip package and packaging method
A chip package and a packaging method are provided, which relates to the field of communications technologies, and is invented to implement high-frequency...
US-9,484,310 Invisible dummy features and method for forming the same
A plurality of first miniature elements of an overlay mark is formed in a first layer. A plurality of second miniature elements of the overlay mark is formed in...
US-9,484,309 Light emitting device and method for manufacturing light emitting device
A light emitting device (10) includes light emitting elements (12), conductor wirings (14), and alignment marks (18) formed on a substrate (11). The alignment...
US-9,484,308 Semiconductor device
A semiconductor device includes a substrate including a pad and an alignment feature disposed over the substrate, a passivation disposed over the substrate and...
US-9,484,307 Fan-out wafer level packaging structure
Described herein is a semiconductor device and the manufacturing method thereof, wherein the semiconductor device includes a first die including a first pad and...
US-9,484,306 MOSFET with asymmetric self-aligned contact
A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a...
US-9,484,305 Offset contacts for reduced off capacitance in transistor switches
Systems, apparatuses and methods for reduced OFF capacitance in switching devices are disclosed. A semiconductor die may include a semiconductor substrate,...
US-9,484,304 Semiconductor device and method for producing same
In order to prevent the detachment of a film which is a constituent part of an interlayer-insulating film, and to prevent a decline in the device properties of...
US-9,484,303 Stress tuning for reducing wafer warpage
An integrated circuit structure includes a substrate, a plurality of low-k dielectric layers over the substrate, a first dielectric layer over the plurality of...
US-9,484,302 Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device comprises a workpiece including a conductive...
US-9,484,301 Controlled metal extrusion opening in semiconductor structure and method of forming
Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor...
US-9,484,300 Device resulting from printing minimum width semiconductor features at non-minimum pitch
Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the...
US-9,484,299 Signal line connection structure and apparatus using the same
The present disclosure relates to a signal line connection structure and apparatuses using the same. The signal line connection structure according to an...
US-9,484,298 Non-volatile memory device
A non-volatile memory device includes a first electrode layer extending in a first direction and a first channel body extending through the first electrode...
US-9,484,297 Semiconductor device having non-magnetic single core inductor and method of producing the same
Integrated circuits with single core inductors and methods for producing them are provided. Embodiments include forming a trench in a dielectric layer; forming...
US-9,484,296 Self-aligned integrated line and via structure for a three-dimensional semiconductor device
At least one via level dielectric layer and at least one line level dielectric layer are sequentially formed over an array of device structures. Conductive line...
US-9,484,295 Image forming apparatus, chip, and chip package to reduce cross-talk between signals
An image forming apparatus including an engine unit to perform an image forming operation, and a board unit to control the engine unit. The board unit includes...
US-9,484,294 Semiconductor device and method of manufacturing the same
A semiconductor device of the present invention includes a bonding target and an electrode terminal bonded to the bonding target. The electrode terminal and the...
US-9,484,293 Semiconductor devices with close-packed via structures having in-plane routing and method of making same
The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side...
US-9,484,292 Semiconductor package and method of forming the same
A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including...
US-9,484,291 Robust pillar structure for semicondcutor device contacts
Methods and systems for a robust pillar structure for a semiconductor device contacts are disclosed, and may include processing a semiconductor wafer comprising...
US-9,484,290 Electronic system with a composite substrate
A composite substrate made of a conductive pattern structure mounted on a lead frame is used for an electronic system package. High heat generated electronic...
US-9,484,289 Semiconductor device with heat spreader
A semiconductor device includes a package body, a semiconductor die embedded in the package body and a heat spreader attached to a top surface of the package...
US-9,484,288 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of...
US-9,484,287 Semiconductor device and a method of manufacturing the same
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a...
US-9,484,286 Semiconductor device and a method of manufacturing the same
A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a...
US-9,484,285 Interconnect structures for wafer level package and methods of forming same
A method for forming a device package includes forming a molding compound around a die and laminating a polymer layer over the die. A top surface of the die is...
US-9,484,284 Microfluidic impingement jet cooled embedded diamond GaN HEMT
A MMIC power amplifier circuit assembly comprised of a SiC substrate having a plurality of microchannels formed therein, where a diamond layer is provided...
US-9,484,283 Modular jet impingement cooling apparatuses with exchangeable jet plates
Modular cooling apparatuses are disclosed. In one embodiment, a cooling apparatus includes an inlet manifold, a jet plate manifold, a plurality of jet plates, a...
US-9,484,282 Resin-sealed semiconductor device
There is provided a resin-sealed semiconductor device (BGA type semiconductor device) whose heat dissipating characteristic is improved, so that it is prevented...
US-9,484,281 Systems and methods for thermal dissipation
A package on package semiconductor structure includes a first package positioned above a first surface of a substrate, a second package positioned above the...
US-9,484,280 Semiconductor device and method of manufacturing a semiconductor device
A semiconductor device is provided, wherein the semiconductor device comprises a carrier, wherein the carrier comprises a first portion configured to hold a...
US-9,484,279 Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die
A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited...
US-9,484,278 Semiconductor package and method for producing the same
A semiconductor package includes a housing having a bottom surface and an upper surface and a solder pad arranged in the bottom surface of the housing. The...
US-9,484,277 Materials, structures and methods for microelectronic packaging
Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass...
US-9,484,276 Semiconductor mounting device and method for manufacturing semiconductor mounting device
A semiconductor mounting device including a first substrate having insulation layers, conductor layers formed on the insulation layers, and via conductors...
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