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Patent # Description
US-9,484,275 Semiconductor module for high pressure applications
A semiconductor module comprising a plurality of electrically conductive top plates, an electrically conductive base plate, a plurality of semiconductor chips...
US-9,484,274 Methods for reducing semiconductor substrate strain variation
Embodiments of the disclosure provide methods and system for correcting lithographic film stress/strain variations on a semiconductor substrate using laser...
US-9,484,273 Apparatus for measuring impurities on wafer and method of measuring impurities on wafer
Provided are an apparatus for measuring impurities on a wafer and a method of measuring impurities on a wafer. The apparatus includes: a wafer aligning device...
US-9,484,272 Methods for fabricating strained gate-all-around semiconductor devices by fin oxidation using an undercut...
Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a...
US-9,484,271 Semiconductor device and method of manufacturing the same
Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region...
US-9,484,270 Fully-depleted silicon-on-insulator transistors
A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold...
US-9,484,269 Structure and method to control bottom corner threshold in an SOI device
Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a...
US-9,484,268 Semiconductor device and production method
The object to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit is achieved by forming an inverter which comprises:...
US-9,484,267 Stacked nanowire devices
A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is...
US-9,484,266 Complementary heterogeneous MOSFET using global SiGe substrate and hard-mask memorized germanium dilution for nFET
A method includes providing a substrate that underlies a layer of SiGe; forming a plurality of fins in the layer of SiGe. Each formed fin has a fin shape and...
US-9,484,265 Structure and method for semiconductor device
A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate having first and second device regions. The...
US-9,484,264 Field effect transistor contacts
A first field effect transistor (FET) device includes a first gate over a first channel region of a first fin arranged on a substrate, a second gate of a second...
US-9,484,263 Method of removing a hard mask on a gate
A method of removing a hard mask on a gate includes forming a first gate structure and a second gate structure. The first gate structure includes a first gate,...
US-9,484,262 Stressed channel bulk fin field effect transistor
Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function...
US-9,484,261 Formation of self-aligned source for split-gate non-volatile memory cell
A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first...
US-9,484,260 Heated carrier substrate semiconductor die singulation method
In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the...
US-9,484,259 Semiconductor device and method of forming protection and support structure for conductive interconnect structure
A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact...
US-9,484,258 Method for producing self-aligned vias
A method for producing self-aligned vias (SAV) is provided. Embodiments include forming a ILOS layer over a dielectric layer; forming pairs of spacers over the...
US-9,484,257 Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming...
US-9,484,256 Pure boron for silicide contact
A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench...
US-9,484,255 Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts
An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device...
US-9,484,254 Size-filtered multimetal structures
A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in...
US-9,484,253 Signal line fabrication method, array substrate fabrication method, array substrate and display device
Embodiments of the disclosure provide a signal line fabrication method, an array substrate fabrication method, an array substrate and a display device. The...
US-9,484,252 Integrated circuits including selectively deposited metal capping layers on copper lines and methods for...
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes...
US-9,484,251 Contact integration for reduced interface and series contact resistance
Methods of lightly implanting platinum, iridium, osmium, erbium, ytterbium, dysprosium, and gadolinium in semiconductor material in shallow depths by...
US-9,484,250 Air gap contact formation for reducing parasitic capacitance
A functional gate structure is located on a surface of a semiconductor material portion and including a U-shaped gate dielectric portion and a gate conductor...
US-9,484,249 Method of manufacturing semiconductor device
A technique capable of suppressing a variation in a characteristic of a semiconductor device includes: (a) polishing a substrate including: a first insulating...
US-9,484,248 Patternable dielectric film structure with improved lithography and method of fabricating same
A method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric...
US-9,484,247 Semiconductor device having stable structure and method of manufacturing the same
The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured...
US-9,484,246 Buried signal transmission line
A buried conductive layer is formed underneath a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A deep isolation trench laterally...
US-9,484,244 Structures and methods for forming fin structures
Structures and methods are provided for forming fin structures. A first fin structure is formed on a substrate. A shallow-trench-isolation structure is formed...
US-9,484,243 Processing chamber with features from side wall
A processing chamber having a chamber housing with a top and sidewalls is provided. The processing chamber has a seal for connecting the sidewalls of the...
US-9,484,242 Fluid pressure cylinder
A fluid pressure cylinder includes a displacement member, which is displaceable on an end side of a body, and a connecting body, which is connected to a piston...
US-9,484,241 Device for holding multiple semiconductor devices during thermocompression bonding and method of bonding
Disclosed is a device for holding a plurality of semiconductor devices during thermocompression bonding, comprising: a body; a plurality of support surfaces at...
US-9,484,240 Film adhesive, dicing tape with film adhesive, method of manufacturing semiconductor device, and semiconductor...
The present invention provides a film adhesive that can prevent a thermal effect to a semiconductor wafer and that can suppress warping of the semiconductor...
US-9,484,239 Sacrificial carrier dicing of semiconductor wafers
Mechanisms are provided for sacrificial carrier dicing of semiconductor wafers. A bottom layer of a semiconductor wafer is bonded to a top layer of a...
US-9,484,238 Attachment method
An attachment method including an overlapping step of overlapping a support plate over a substrate under a reduced pressure environment; a temporary fixing step...
US-9,484,237 Mass transfer system
Micro pick up arrays for transferring micro devices from a carrier substrate are disclosed. In an embodiment, a micro pick up array includes a compliant contact...
US-9,484,236 Joining method and joining system
This joining method of joining a target substrate and a support substrate includes: an adhesive coating operation that includes coating the target substrate or...
US-9,484,235 Substrate processing apparatus, substrate transfer method and storage medium
In a substrate processing apparatus 1 which performs a process on a substrate W, each of multiple processing modules 2 includes at least a first processing...
US-9,484,234 Processing station for planar substrates and method for processing planar substrates
A processing station for two-dimensional substrates including at least two processing units and at least two conveyor lines for substrates arranged in parallel...
US-9,484,233 Carousel reactor for multi-station, sequential processing systems
A reactor for processing a plurality of substrates includes P processing station assemblies arranged symmetrically around an axis, where P is an integer greater...
US-9,484,232 Zone temperature control structure
A zone temperature control structure which has two or more zone of which surface temperatures are controlled to different temperatures, respectively. The...
US-9,484,231 Temperature controller for semiconductor manufacturing equipment, method for calculating PID constants in...
A temperature adjustment system configured to adjust the temperature of a fluid used in a semiconductor manufacturing apparatus includes: a heat exchanger...
US-9,484,230 Substrate liquid processing apparatus
A substrate liquid processing apparatus of the present invention includes a process-liquid supply unit selectively supplying a plurality of types of...
US-9,484,229 Device and method for processing wafer-shaped articles
A device for processing wafer-shaped articles includes a spin chuck for holding and rotating a wafer-shaped article about a rotation axis and at least one...
US-9,484,228 Simultaneous independently controlled dual side PCB molding technique
Molding assemblies and methods for dual side package molding are described. In an embodiment, a molding compound is injected into a front cavity with a first...
US-9,484,227 Dicing in wafer level package
A method includes placing a first device die and a second device die over a carrier, with a scribe line between the first device die and the second device die....
US-9,484,226 Methods for controlling warpage in packaging
A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and...
US-9,484,225 Method for packaging circuits
A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base...
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