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Patent # Description
US-9,484,123 Conductive sealant compositions
Embodiments of the present disclosure are directed to sealant compositions including a base composition with at least one sulfur-containing polymer, a curing...
US-9,484,122 Post-accident fission product removal system and method of removing post-accident fission product
A post-accident fission product removal system may include an air mover, a filter assembly, and/or an ionization chamber. The air mover may be configured to...
US-9,484,121 System and method for storing energy in a nuclear power plant
A method for storing the energy of a nuclear power plant in which the nuclear core is cooled by gases or liquid heat transfer media. The hot heat transfer...
US-9,484,120 Method for annulus spacer detection and repositioning in nuclear reactors
The present invention provides an apparatus for detecting and/or repositioning annulus spacers used to maintain the position of a pressure tube within a...
US-9,484,119 Liquid nitrogen emergency cooling system for nuclear power plants
A reactor cooling system for cooling a nuclear reactor using nitrogen comprising a refrigeration unit for cooling and compressing nitrogen gas into liquid...
US-9,484,118 BWR nuclear fuel assembly with non-retained partial length fuel rods
A nuclear fuel assembly for a boiling water reactor is provided. The nuclear fuel assembly includes a base, a head and a bundle of full length fuel rods and...
US-9,484,117 Semiconductor memory device having compression test mode
A semiconductor memory device having a compression test mode is provided. The semiconductor memory device comprises a memory unit, i test pads, a timing...
US-9,484,116 Test system
At least one general-purpose server is connected to a PE module via Ethernet (trademark). A control unit of the PE module controls a PE circuit and multiple...
US-9,484,115 Power savings via selection of SRAM power source
A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary...
US-9,484,114 Decoding data using bit line defect information
A data storage device includes a memory including a plurality of storage elements configured to store data. The plurality of storage elements includes a first...
US-9,484,113 Error-correction coding for hot-swapping semiconductor devices
A memory read operation is directed at a group of semiconductor devices from which a first semiconductor device has been removed. An error in data for the...
US-9,484,112 Liquid crystal display and shift register thereof
The present invention provides a liquid crystal display and a shift register thereof. Each shift register unit of the shift register comprises a storage...
US-9,484,111 Bidirectional scanning GOA circuit
A GOA circuit for use in LCD applications is disclosed, and the GOA circuit includes multiple cascaded GOA units, each of which includes a pull-up control...
US-9,484,110 Mask-programmed read only memory with enhanced security
A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality...
US-9,484,109 Memory cell and memory device
The memory cell of a memory device comprises a MOS capacitor having a n-type gate and a n-type well, a first switch to temporarily apply a breakthrough voltage...
US-9,484,108 Integrated circuit, semiconductor memory device, and operating method thereof
An integrated circuit includes an internal circuit including a input/output unit suitable for inputting/outputting data, and a voltage supplying circuit...
US-9,484,107 Dual non-volatile memory cell comprising an erase transistor
The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating...
US-9,484,106 Nonvolatile semiconductor memory
A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory...
US-9,484,105 Nonvolatile semiconductor memory device
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second...
US-9,484,104 Nonvolatile memory system with block managing unit and method of operating the same
According to example embodiments, a nonvolatile memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device...
US-9,484,103 Electronic storage device
A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.
US-9,484,102 Semiconductor device and method of operating the same
A method of operating the semiconductor device includes performing an erase operation on a plurality of memory cells, performing a back-tunneling operation by...
US-9,484,101 Methods of programming memories
Methods of programming memories include applying a first plurality of programming pulses to the group of memory cells to program first data to the group of...
US-9,484,100 Memory devices having source lines directly coupled to body regions and methods
Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body...
US-9,484,099 Three dimensional semiconductor memory device with line sharing scheme
A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers over a substrate and an operation circuit...
US-9,484,098 Smart reread in nonvolatile memory
A population of memory cells are programmed and an indicator of a first number of the memory cells programmed to a first state is recorded. Subsequently, a...
US-9,484,097 Multipage program scheme for flash memory
A circuit and method for programming multiple bits of data to flash memory cells in a single program operation cycle. Multiple pages of data to be programmed...
US-9,484,096 Ternary content-addressable memory
A ternary content-addressable memory comprises a first switch, a first static random-access memory cell, a second switch and a second static random-access...
US-9,484,095 TCAM providing efficient move contents operation
An embodiment of the invention includes a Ternary Content Addressable Memory (TCAM) that includes a group of TCAM block. Each TCAM block stores a number of...
US-9,484,094 Control method of resistive random-access memory
A control method of a resistive random-access memory is provided. Firstly, an action is performed on the resistive random-access memory, so that the resistive...
US-9,484,093 Controlling adjustable resistance bit lines connected to word line combs
Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage...
US-9,484,092 Intrinsic vertical bit line architecture
Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage...
US-9,484,091 Resistance change memory
According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a...
US-9,484,090 Read and write methods for a resistance change non-volatile memory device
A selection circuit that selects a memory cell from a memory cell array and a read circuit for reading a resistance state of a resistance change element in the...
US-9,484,089 Dual polarity read operation
A data storage device includes a memory die and a controller coupled to the memory die. The memory die includes a resistive memory and read/write circuitry...
US-9,484,088 Permutational memory cells
Various embodiments include at least one resistance change memory (RCM) cell, In one embodiment, three or more pairs of electrical contacts are coupled to the...
US-9,484,087 Multi-bit memory elements, memory devices including the same, and methods of manufacturing the same
In one embodiment, the memory element may include a first electrode, a second electrode spaced apart from the first electrode, a memory layer between the first...
US-9,484,086 Determination of word line to local source line shorts
A number of techniques determine defects in non-volatile memory arrays, which are particularly applicable to 3D NAND memory, such as BiCS type. Word line to...
US-9,484,085 Static memory apparatus and static memory cell thereof
A static memory apparatus and a static memory cell thereof are provided. The static memory cell includes a data latch circuit, a data write-in circuit and a...
US-9,484,084 Pulling devices for driving data lines
A circuit includes a first data line, a second data line, a first pulling device, a second pulling device, a third pulling device, and a fourth pulling device....
US-9,484,083 Semiconductor device and semiconductor storage device
A semiconductor device includes a circuit block that is switchable between selection and non-selection, and a leakage current control circuit disposed between...
US-9,484,082 Method of operating semiconductor memory device with floating body transistor using silicon controlled...
Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are...
US-9,484,081 Semiconductor device having transistor and semiconductor memory device using the same
Semiconductor device capable of preventing off-leakage of the transistor may include a pulse voltage generator configured to generate a pulse voltage, and a...
US-9,484,080 High-bandwidth memory application with controlled impedance loading
A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and...
US-9,484,079 Memory device and memory system including the same
A memory device may include a temperature sensor suitable for generating temperature information and a smart refresh circuit suitable for activating a smart...
US-9,484,078 Providing services from a remote computer system to a user station over a communications network
A method includes receiving the second information at the remote computer system during a second user initiated communication session from the user station...
US-9,484,077 Providing services from a remote computer system to a user station over a communications network
A method includes receiving first information at a remote computer system during a first user-initiated communication session for a user station not previously...
US-9,484,076 Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features
Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include...
US-9,484,075 Semiconductor device
A semiconductor device includes data terminal, unit buffers which drive the data terminal and the impedance of which can be adjusted, and control circuits which...
US-9,484,074 Current mode sense amplifier with load circuit for performance stability
Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled...
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