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Phase-locked loop with frequency bounding circuit
A phase-locked loop (PLL) for generating an oscillating signal includes a frequency bounding circuit. When a frequency of the oscillating signal is greater than...
Described herein is a self-biased oscillator. The self-biased oscillator comprises a first differentiator with adjustable resistance or capacitance, the first...
Delay lock loop
A delay lock loop including a selection unit, a delay unit, an elimination unit, and a phase detection unit is provided. The selection unit receives a...
Glitch less delay circuit for real-time delay adjustments
An apparatus is disclosed in which a clock signal may propagate through a delay circuit. The delay circuit may include a first and a second delay stage, in...
Fractional N-PLL circuit, oscillator, electronic device, and moving object
In order to appropriately set an operation range of a voltage controlled oscillator without excessively increasing a frequency at which delta-sigma modulation...
Auto frequency calibration for a phase locked loop and method of use
An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference...
Cancellation of delta-sigma quantization noise within a fractional-N PLL
with a nonlinear time-to-digital converter
A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to...
Method and apparatus for gals system
Aspects of the disclosure provide a system. The system includes a first functional circuit, a first clock generator, a second functional circuit, and a second...
Parameter control method for integrated circuit and integrated circuit
using the same
A parameter control method for an integrated circuit and an integrated circuit using the same are provided. The method includes the steps of: providing a...
Robust, low power, reconfigurable threshold logic array
A field programmable threshold-logic array (FPTLA) includes a number of threshold logic gates and a number of programmable interconnect elements. Each one of...
Configurable IC having a routing fabric with storage elements
Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a...
High-speed level-shifting multiplexer
Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of...
Configurable clock network for programmable logic device
In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic...
Fine grain programmable gate architecture with hybrid logic/routing
element and direct-drive routing
An apparatus is disclosed herein for a programmable gate architecture with hybrid logic/routing circuitry. In one embodiment, a programmable gate array...
Low-noise, temperature-insensitive, voltage or current input, analog front
AFE circuitry handles both voltage and current input signals. In one embodiment, both a voltage path and a current path are provided from the input. Switching...
Shift register circuit
A shift register circuit includes a pull-down circuit, pull-down control circuit, a driving unit, a primary pull-down circuit and a gate driver circuit. The...
A sensing circuit includes a delay chain and a decoder. The delay chain includes at least one delay unit, at least one cascading switch, and at least one...
Power reducing logic and non-destructive latch circuits and applications
In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the...
A programmable analog device and an analog device that can retain data even when supply of a power supply potential is interrupted and consumes less power. In a...
Low power driver with programmable output impedance
A programmable low power driver permits an output impedance of the driver to be programmed. Programmability permits the driver output impedance to match an...
Capacitance sensing circuits, methods and systems having conductive touch
A capacitance sense device can include a plurality of sense electrodes; a nonconductive structure comprising first regions formed over the sense electrodes and...
User interface panel
A user interface panel includes a touch sensor having one or more sensing electrodes and a user interface substrate disposed on a circuit carrier substrate. The...
Apparatus and method for transmitting an analog signal, and analog signal
Disclosed are an apparatus and a method for transmitting an analog signal, and an analog signal multiplexer. The apparatus comprises a photocoupler to receive...
Rapid cutoff device and operation method for SCR AC switches
A rapid cutoff device includes a thyristor AC switch for supplying an AC current from a first AC circuit to a second AC circuit. A serially-connected circuit of...
Control circuit of semiconductor switching element
A control circuit of a semiconductor switching element includes a gate driving circuit and a negative power source circuit. The gate driving circuit drives the...
Electronic device and operation method thereof
An electronic device includes a transmission interface, a switch unit and a control unit. The transmission interface includes a signal reference contact and a...
Gate drive control system for SiC and IGBT power devices
A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and a comparator that compares output signal of the power...
A drive device that drives a semiconductor switching device includes a capacitor, an output selection unit that selects whether or not to supply a charge of the...
Power-on-reset and supply brown out detection circuit with programmability
A low-power wideband Power-on-Reset (PoR) and supply brown out detection circuit is proposed, wherein a technique for accurately controlling the PoR trip points...
System and method for selectively coupled parasitic compensation for input
referred voltage offset in...
A system and method are provided for selectively coupled parasitic compensation for voltage offset in an electronic circuit. At least one compensation cell is...
Dynamic shutdown protection circuit
Systems, circuits, and methods for operating an Insulated-Gate Bipolar Transistor (IGBT) are provided. A switching circuit is described that includes a first...
Insulated-gate type device driving circuit
An insulated-gate type device driving circuit for driving an insulated-gate semiconductor element based on a gate signal inputted from the outside includes a...
Pulse width modulation with effective high duty resolution
A pulse width modulation (PWM) signal generator generates a PWM signal having a specified effective PWM duty resolution for a corresponding cycle window. The...
Method and circuit for detecting USB 3.0 LFPS signal
A system and method for efficient detection of Low Frequency Periodic Signaling (LFPS) input signals. A receiver receives two input differential signals that...
Digital pulse reject counter
A system and method are provided for filtering noise from a pulsed input signal comprising cyclically producing a change in an output signal only if changes in...
Glitch-free clock switching circuit using Muller C-elements
A clock switching circuit includes first and second clock lines, first and second selection lines, and first through fourth Muller C-elements. The Muller...
A semiconductor device includes a first variable delay circuit that delays inputted multiphase signals according to a delay control signal, a selection circuit...
System and method for integrated circuit clock distribution
An embodiment integrated circuit (IC) clock distributor system includes a first IC. The first IC includes a clock synchronizer circuit and a clock generator...
Driver circuit with gate clamp supporting stress testing
A generator circuit is coupled to apply a control signal to the gate terminal of a power transistor driving an output node. A reference voltage is generated...
Programmable delay circuit for low power applications
Programmable delay circuits are described herein according to embodiments of the present disclosure. In one embodiment, a delay circuit comprises a plurality of...
Apparatus and method for generating quadrupled reference clock from single
ended crystal oscillator
A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates,...
Area efficient multi bit flip flop topologies
The invention is an intelligent connection of the internal scan logic in a multi-bit flip-flop register. Individual bits in this register are connected in a...
A latch circuit is based on a master-slave cross-coupled inverter pair configuration. The inverters of the slave circuit are coupled to a high voltage rail and...
Redundant clock transition tolerant latch circuit
Embodiments of a latch circuit and a method of operating a latch circuit are described. In one embodiment, a latch circuit includes an input terminal configured...
Apparatuses, methods, and systems for dense circuitry using tunnel field
Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first...
Dynamic circuitry using pulse amplification to reduce metastability
Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying...
High-resolution oscillator having wide frequency range
In one embodiment, a voltage-controlled oscillator has a ring of delay stages and power-regulating circuitry regulating power to each delay stage. Each delay...
Programmable synchronous clock divider
A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on...
Load transient asynchronous boost for pulse width modulation modulator
A pulse width modulation controller (PWM) is disclosed which has a MOSFET (15) responsive to the error voltage (Verror) signal from the PWM amplifier (17) to...
Implementing adaptive control for optimization of pulsed resonant drivers
A method and circuit are provided for implementing adaptive control for optimization of pulsed resonant drivers, and a design structure on which the subject...