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Patent # Description
US-9,490,270 Array substrate and manufacturing method thereof, and display device including the array substrate
An array substrate and manufacturing method thereof and a display device having the array substrate are provided. The array substrate includes a non-pixel...
US-9,490,269 Display device
Disclosed are a display device and the manufacturing method thereof. In the display device, the pixel unit of the display substrate comprises: a gate line...
US-9,490,268 Semiconductor device and display device including the semiconductor device
A semiconductor device including a transistor and a connection portion is provided. The transistor includes a gate electrode, a first insulating film over the...
US-9,490,267 Semiconductor device
A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor...
US-9,490,266 Array substrate and method for producing the same and display apparatus
Embodiments of the present invention relate to the display field and provide an array substrate, a method for producing the same and a display apparatus, for...
US-9,490,265 Semiconductor device and method for fabricating the same
A semiconductor device is disclosed. The semiconductor device includes: a substrate having a metal-oxide semiconductor (MOS) transistor thereon, and an oxide...
US-9,490,264 Device having a contact between semiconductor regions through a buried insulating layer, and process for...
The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material...
US-9,490,263 Semiconductor device and method of forming the same
A semiconductor device includes a substrate on which a plurality of logic cells are provided, and a plurality of active portions provided on the substrate and...
US-9,490,262 Selective removal of charge-trapping layer for select gate transistor and dummy memory cells in 3D stacked memory
Fabrication techniques for a three-dimensional stack memory device remove the charge-trapping material from the select gate transistors and the dummy memory...
US-9,490,261 Minimizing disturbs in dense non volatile memory arrays
A nitride read only memory (NROM) array includes a silicon substrate having trenches therein, a plurality of polysilicon bit lines deposited in the trenches and...
US-9,490,260 Method for fabricating a semi-floating gate transistor
A semi-floating gate transistor structure includes a substrate, a first N-well region and a second N-well region separated from each other in the substrate, and...
US-9,490,259 Anti-fuse, anti-fuse array and method of operating the same
An anti-fuse, an anti-fuse array and a method of operating the same are disclosed. The anti-fuse array includes: an active region formed in a semiconductor...
US-9,490,258 Semiconductor device and method for fabricating the same
Provided are a semiconductor device and a method for fabricating the same. The semiconductor device comprises a first fin type active pattern formed on a...
US-9,490,257 Deep trench polysilicon fin first
After forming a recessed conductive material portion over a deep trench capacitor located in a lower portion of a deep trench embedded in a substrate, a hard...
US-9,490,256 Semiconductor devices having contact plugs overlapping associated bitline structures and contact holes and...
A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the...
US-9,490,255 Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments
An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first...
US-9,490,254 Fin sidewall removal to enlarge epitaxial source/drain volume
A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material...
US-9,490,253 Gate planarity for finFET using dummy polish stop
A method for forming a semiconductor device includes depositing a dielectric layer over fins formed in a semiconductor substrate. The dielectric layer includes...
US-9,490,252 MIM capacitor formation in RMG module
A method is provided for forming a metal-insulator-metal capacitor in a replacement metal gate module. The method includes providing a gate cap formed on a...
US-9,490,251 Diode-connected bipolar junction transistors and electronic circuits including the same
A diode-connected bipolar junction transistor includes a common collector region of a first conductivity, a common base region of a second conductivity disposed...
US-9,490,250 Half-bridge circuit with a low-side transistor and a level shifter transistor integrated in a common...
A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal. The half-bridge circuit further...
US-9,490,249 Antenna effect discharge circuit and manufacturing method
An antenna effect discharge circuit is described for a device having patterned conductor layers, which may be exposed to charge inducing environments during a...
US-9,490,248 Power cell, power cell circuit for a power amplifier and a method of making and using a power cell
A power cell including an isolation region having a first dopant type formed in a substrate. The power cell further includes a bottom gate having a second...
US-9,490,247 Semiconductor device and method for manufacturing same
An IGBT (50) includes a p.sup.+ collector region (3) and an n.sup.-- drift region (1), in which a first transistor (TR1) and a second transistor (TR2) are...
US-9,490,246 Semiconductor device
A P-type epitaxial growth layer is formed on a P-type semiconductor substrate with an N-type buried region and a P-type buried region interposed therebetween. A...
US-9,490,245 Circuit and layout for a high density antenna protection diode
A MOS device for reducing an antenna effect is provided. The MOS device includes a diode including a first nMOS transistor having a first nMOS transistor...
US-9,490,244 Integrated circuit comprising a clamping structure and method of adjusting a threshold voltage of a clamping...
An integrated circuit comprises a load transistor including first and second load terminals and a load control terminal. The integrated circuit further...
US-9,490,243 Semiconductor device comprising an ESD protection device, an ESD protection circuitry, an integrated circuit...
A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are...
US-9,490,242 Semiconductor device and semiconductor package
A semiconductor device capable of ensuring a withstand voltage of a transistor and reducing a forward voltage of a Schottky barrier diode in a package with the...
US-9,490,241 Semiconductor device comprising a first inverter and a second inverter
A semiconductor device which is downsized while a short-channel effect is suppressed and whose power consumption is reduced is provided. A downsized SRAM...
US-9,490,240 Film interposer for integrated circuit devices
In one embodiment, a stack device comprising a film interposer of a polyimide film material, for example, is assembled. In accordance with one embodiment of the...
US-9,490,239 Solid state transducers with state detection, and associated systems and methods
Solid state transducers with state detection, and associated systems and methods are disclosed. A solid state transducer system in accordance with a particular...
US-9,490,237 Semiconductor package including a plurality of chips
A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and...
US-9,490,236 Light-emitting device and lighting device provided with the same
A light-emitting device capable of ensuring an electric connection between a light-emitting element and an electrode without generating any problem in practical...
US-9,490,235 Light emitting devices, systems, and methods
Light emitting devices, systems, and methods are disclosed. In one embodiment a light emitting device can include an emission area having one or more light...
US-9,490,234 Alternative current light-emitting systems
A light-emitting system is introduced herein. The light-emitting system includes an insulating substrate and a plurality of light-emitting units ...
US-9,490,233 Fingerprint recognition semiconductor device and semiconductor device
A fingerprint recognition semiconductor device includes an insulation layer, a wiring pattern formed on a lower surface of the insulation layer, and a sensor...
US-9,490,232 Electronic apparatus and method for fabricating the same
An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and...
US-9,490,231 Manufacturing method of semiconductor device and semiconductor device thereof
A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a...
US-9,490,230 Selective die electrical insulation by additive process
Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a...
US-9,490,229 Semiconductor device connected by anisotropic conductive film
Provided is a semiconductor device, including an anisotropic conductive film connecting the semiconductor device, the anisotropic conductive film having a...
US-9,490,228 Anisotropic conductive film including conductive adhesive layer and semiconductor device connected by the same
An anisotropic conductive film includes a conductive adhesive layer including conductive particles and insulating particles, and an insulating adhesive layer...
US-9,490,227 Low-noise flip-chip packages and flip chips thereof
A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down...
US-9,490,226 Integrated device comprising a heat-dissipation layer providing an electrical path for a ground signal
Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first...
US-9,490,225 Package structure and fabrication method thereof
A package structure is provided, which includes: a substrate having opposite top and bottom surfaces and a plurality of conductive pads and a plurality of...
US-9,490,224 Semiconductor device and manufacturing method thereof
A resin sealed semiconductor device includes a semiconductor element having a plurality of metal plated plastic particle core or metal particle core micro-balls...
US-9,490,223 Structure to prevent deep trench moat charging and moat isolation fails
A semiconductor structure is provided that includes a semiconductor on insulator (SOI) substrate comprising a bottom semiconductor layer, an epitaxial...
US-9,490,222 Wire bond wires for interference shielding
Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper...
US-9,490,221 Semiconductor device having multiple magnetic shield members
A semiconductor device includes a wiring substrate, a lower magnetic shield member, a semiconductor chip, and an upper magnetic shield member. The lower...
US-9,490,220 Redistribution structures for microfeature workpieces
Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having...
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