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Patent # Description
US-9,490,219 Semiconductor package with shielding member and method of manufacturing the same
This invention provides a semiconductor package, including a substrate, a plurality of semiconductor elements disposed on the substrate, at least one shielding...
US-9,490,218 Method for manufacturing semiconductor device
To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark...
US-9,490,217 Overlay marks and semiconductor process using the overlay marks
An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in...
US-9,490,216 Semiconductor device and semiconductor package
Provided are a semiconductor device and a semiconductor package. The semiconductor device includes semiconductor device includes a semiconductor substrate...
US-9,490,215 Organic light-emitting display device and method for manufacturing organic light-emitting display device
Provided are an organic light-emitting display device and a method for manufacturing the same. A flexible substrate of the organic light-emitting display device...
US-9,490,214 Semiconductor device and method of fabricating the same
A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a...
US-9,490,213 Semiconductor device and manufacturing method thereof
The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including...
US-9,490,212 High quality electrical contacts between integrated circuit chips
Methods and structures of connecting at least two integrated circuits in a 3D arrangement by a zigzag conductive chain are disclosed. The zigzag conductive...
US-9,490,211 Copper interconnect
A method of filling features in a dielectric layer is provided. A pure Co or pure Ru adhesion layer is deposited against surfaces of the features, wherein the...
US-9,490,210 Electrical interconnection structure and fabrication method thereof
An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and...
US-9,490,209 Electro-migration barrier for Cu interconnect
Integrated circuit devices and method of forming them. The devices include a dielectric barrier layer formed over a copper-containing metal interconnect...
US-9,490,208 Semiconductor device
A semiconductor device includes a semiconductor chip, a dielectric substrate, and bonding wires. The dielectric substrate includes wiring patterns formed on a...
US-9,490,207 Semiconductor device having a copper wire within an interlayer dielectric film
The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a...
US-9,490,206 Electrical device and fabrication method
An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure...
US-9,490,205 Integrated circuit interconnects and methods of making same
A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is...
US-9,490,204 Noise shielding techniques for ultra low current measurements in biochemical applications
A device having an integrated noise shield is disclosed. The device includes a plurality of vertical shielding structures substantially surrounding a...
US-9,490,203 Capacitor in post-passivation structures and methods of forming the same
A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying...
US-9,490,202 Self-aligned airgap interconnect structures
Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures...
US-9,490,201 Methods of forming under device interconnect structures
Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a...
US-9,490,200 Semiconductor device
Disclosed is a semiconductor device having a structure capable of reducing the self-inductance of internal wiring. The semiconductor device includes: a lower...
US-9,490,199 Interposer with programmable matrix for realizing configurable vertical semiconductor package arrangements
An interposer for establishing a vertical connection between semiconductor packages includes an electrically insulating substrate having a first main side and a...
US-9,490,198 Transmitting and receiving package
Provided is a transmitter and receiver package including an interposer substrate including a top surface, a bottom surface facing the top surface, and a...
US-9,490,197 Three dimensional organic or glass interposer
A three-dimensional organic structure or glass interposer structure and methods of manufacture are disclosed. The method includes forming lined metal vias in a...
US-9,490,196 Multi die package having a die and a spacer layer in a recess
Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions...
US-9,490,195 Wafer-level flipped die stacks with leadframes or metal foil interconnects
An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with...
US-9,490,194 Semiconductor device
The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse...
US-9,490,193 Electronic device with multi-layer contact
The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and...
US-9,490,192 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a through via, a molding surrounding the through via, a dielectric layer disposed over the die, the through via and the...
US-9,490,191 Mounting structure of semiconductor device and method of manufacturing the same
A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first...
US-9,490,190 Thermal dissipation through seal rings in 3DIC structure
A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via,...
US-9,490,189 Semiconductor device comprising a stacked die configuration including an integrated peltier element
A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier...
US-9,490,188 Compute intensive module packaging
A package for a multi-chip module includes a top cold plate and a bottom plate whose perimeters are in thermal communication so the plates together completely...
US-9,490,187 Semiconductor package on which semiconductor chip is mounted on substrate with window
The semiconductor package includes: a substrate having a window and first and second bond fingers arranged over a first surface along a periphery of the window;...
US-9,490,186 Limiting adjustment of polishing rates during substrate polishing
A method of controlling polishing includes polishing a region of a substrate at a first polishing rate, measuring a sequence characterizing values for the...
US-9,490,185 Implant-induced damage control in ion implantation
An ion implantation system is provided having an ion implantation apparatus configured to provide a spot ion beam having a beam density to a workpiece, wherein...
US-9,490,184 Light emitting device and manufacturing method thereof
The light-emitting device has a plurality of light-emitting elements that is mounted on one or more wiring patterns on a substrate. A new light-emitting element...
US-9,490,183 Nondestructive inline X-ray metrology with model-based library method
Described is a method and system for measuring parameters of a structure on a substrate, such as a via or a through-silicon via (TSV) using an imaging X-ray...
US-9,490,182 Measurement of multiple patterning parameters
Methods and systems for evaluating the performance of multiple patterning processes are presented. Patterned structures are measured and one or more parameter...
US-9,490,181 Misalignment/alignment compensation method, semiconductor lithography system, and method of semiconductor...
A misalignment/alignment compensation method for a lithography process includes the steps of: obtaining misalignment data associated with an alignment mark...
US-9,490,180 Method for processing wafer
The invention provides a method for processing a wafer by inserting the wafer into a holding hole of a carrier to hold the wafer, and interposing the carrier...
US-9,490,179 Semiconductor element and semiconductor device
One object is to provide a semiconductor element in which leakage current between a gate electrode and a channel formation region is suppressed even when the...
US-9,490,178 Method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device includes preparing a semiconductor substrate having a first and a second voltage device portion, each including...
US-9,490,177 Integrated circuit devices including stress proximity effects and methods of fabricating the same
An integrated circuit can include first and second FETs of a particular conductivity type on a substrate, wherein a first source/drain region of the first FET...
US-9,490,176 Method and structure for FinFET isolation
A semiconductor device with effective FinFET isolation and method of forming the same are disclosed. The method includes receiving a substrate having an active...
US-9,490,175 Chemical mechanical polishing method for first interlayer dielectric layer
A method for manufacturing a semiconductor device includes providing a semiconductor substrate comprising a low-density region and a high-density region,...
US-9,490,174 Fabricating raised fins using ancillary fin structures
A method of fabricating a raised fin structure including a raised contact structure is provided. The method may include: providing a base fin structure;...
US-9,490,173 Method for processing wafer
A method for processing a wafer including a plurality of chips is provided. The method may include: forming a trench in the wafer between the plurality of...
US-9,490,172 Method for preventing delamination and cracks in group III-V wafers
In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at...
US-9,490,171 Wafer processing method
A wafer is divided along a plurality of crossing division lines to obtain a plurality of individual devices. The division lines are formed on the front side of...
US-9,490,170 Manufacturing method of semiconductor device
A method for manufacturing a semiconductor device includes preparing a structure including a semiconductor substrate having a plurality of semiconductor...
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