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Patent # Description
US-9,490,169 Method of forming vias in silicon carbide and resulting devices and circuits
A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired...
US-9,490,168 Via formation using sidewall image transfer process to define lateral dimension
A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using...
US-9,490,167 Pop structures and methods of forming the same
A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a...
US-9,490,166 Apparatus and method for depositing a layer onto a substrate
Apparatus (1, 26) for depositing a layer (37, 38, 39) on a substrate (2) in a process gas comprises a chuck (3) comprising a first surface (4) for supporting...
US-9,490,165 Reliable interconnect integration scheme
Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as...
US-9,490,164 Techniques for forming contacts for active BEOL
In one aspect, a method for forming a contact to a device is provided which includes the steps of: forming a conformal etch stop layer surrounding the device;...
US-9,490,163 Tapered sidewall conductive lines and formation thereof
A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes conductive lines having sidewalls angled between about...
US-9,490,162 Use of dielectric slots for reducing via resistance in dual damascene process
An integrated circuit may include dual damascene interconnects formed using a via-first dual damascene process or a trench-first dual damascene process. The...
US-9,490,161 Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of...
Multiple threshold voltage devices on hybrid oriented substrates, and methods of manufacturing same are disclosed. A method for manufacturing a semiconductor...
US-9,490,160 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device, the method including providing a substrate; forming a field trench in the substrate; and forming a diffusion...
US-9,490,159 Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes forming isolation layers in a first direction at trenches at isolation regions defined at a...
US-9,490,158 Bond chuck, methods of bonding, and tool including bond chuck
A bonding chuck is discussed with methods of using the bonding chuck and tools including the bonding chuck. A method includes loading a first wafer on first...
US-9,490,157 Semiconductor processing
Semiconductor processing and equipment are disclosed. The semiconductor equipment and processing provide semiconductor wafers with reduced defects.
US-9,490,156 Transfer device for holding an object using a gas flow
A transfer device for holding an object comprises: i) a housing; ii) at least one inlet conduit having an inlet for gas; iii) a plurality of sets of outlet...
US-9,490,155 Wafer processing method using adhesive layer UV curing step and laser modified layer forming step to singulate...
A wafer processing method including a modified layer forming step of applying a laser beam having a transmission wavelength to the wafer along each division...
US-9,490,154 Method of aligning substrate-scale mask with substrate
Methods and systems for alignment of substrate-scale masks are described. The alignment methods presented may improve the uniformity and repeatability of...
US-9,490,153 Mechanical alignment of substrates to a mask
A plurality of masks is attached to the underside of a mask frame. This attachment is made such that each mask can independently move relative to the mask frame...
US-9,490,152 Asymmetrical chamber configuration
A production tool includes a chamber, a heater in the chamber, and a pumping outlet on a side of the heater. A pumping liner is in the chamber and encircling...
US-9,490,151 Substrate processing apparatus and substrate processing method
A substrate processing apparatus performs a predetermined process on a substrate by using a processing gas under a vacuum atmosphere. The substrate processing...
US-9,490,150 Substrate support for substrate backside contamination control
Embodiments of substrate supports are provided herein. In some embodiments, a substrate support may include a first aluminum plate for supporting a substrate,...
US-9,490,149 Chemical deposition apparatus having conductance control
A chemical deposition apparatus having conductance control, which includes a showerhead module having a faceplate and a backing plate, the showerhead module...
US-9,490,148 Adhesion promoter apparatus and method
A structure comprises a substrate having a plateau region and a trench region, a reflecting layer formed over a top surface of the trench region, a first...
US-9,490,147 Stud bump structure and method for manufacturing the same
A stud bump structure and method for manufacturing the same are provided. The stud bump structure includes a substrate, and a first silver alloy stud bump...
US-9,490,146 Semiconductor device with encapsulated lead frame contact area and related methods
A semiconductor device may include an IC, and lead frame contact areas adjacent the IC. Each lead frame contact area may have a lead opening. The semiconductor...
US-9,490,145 Removal of surface passivation
Methods for removing a passivation film from a copper surface can include exposing the passivation film to a vapor phase organic reactant, for example at a...
US-9,490,144 Quaternary ammonium salt compound, composition for forming a resist under layer film, and patterning process
A quaternary ammonium salt compound is represented by the following formula (A-1), ##STR00001## wherein, R.sup.1, R.sup.2, and R.sup.3 each represent an alkyl...
US-9,490,143 Method of fabricating semiconductors
A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The...
US-9,490,142 Cu-low K cleaning and protection compositions
This disclosure relates post chemical mechanical planarization cleaning composition of semiconductor substrate for advanced electronics fabrication and...
US-9,490,141 Method for planarizing semiconductor device
A method for planarizing a semiconductor device includes steps herein. A substrate is provided, on which a stop layer is formed. A trench is formed in the...
US-9,490,140 Method for manufacturing semiconductor device
There are provided methods for manufacturing a semiconductor device including providing a substrate including a metal layer including an oxidized surface layer...
US-9,490,139 Method and apparatus for forming silicon film
Provided is a method of forming a silicon film in a groove formed on a surface of an object to be processed, which includes: forming a first silicon layer on...
US-9,490,138 Method of substrate temperature control during high temperature wet processing
Methods are provided for processing a substrate in single substrate tool. In one embodiment, the method includes providing the substrate in the single substrate...
US-9,490,137 Method for structuring a layered structure from two semiconductor layers, and micromechanical component
A method for structuring a layered structure, for example, of a micromechanical component, from two semiconductor layers between which an insulating and/or etch...
US-9,490,136 Method of forming trench cut
A method includes forming a hard mask (HM) stack over a material layer, which has a first, second, third and fourth HM layers. The method also includes forming...
US-9,490,135 Movable chamber liner plasma confinement screen combination for plasma processing apparatuses
A movable symmetric chamber liner in a plasma reaction chamber, for protecting the plasma reaction chamber, enhancing the plasma density and uniformity, and...
US-9,490,134 Termination structure of semiconductor device and method for manufacturing the same
A termination structure of a semiconductor device is provided. The semiconductor device includes an active area and a termination area adjacent to the active...
US-9,490,133 Etching apparatus
A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration...
US-9,490,132 Substrate, semiconductor device, and method of manufacturing the same
A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor...
US-9,490,131 Control of P-contact resistance in a semiconductor light emitting device
A device according to embodiments of the invention includes a semiconductor device structure (10) including a light emitting region (14) disposed between an...
US-9,490,130 Method of manufacturing three-dimensional semiconductor memory device in which an oxide layer is formed at...
A method of manufacturing a three-dimensional semiconductor memory device comprises forming a thin layer structure by alternately stacking first and second...
US-9,490,129 Integrated circuits having improved gate structures and methods for fabricating same
Integrated circuits with improved gate structures and methods for fabricating integrated circuits with improved gate structures are provided. In an embodiment,...
US-9,490,128 Non-melt thin-wafer laser thermal annealing methods
Methods of annealing a thin semiconductor wafer are disclosed. The methods allow for high-temperature annealing of one side of a thin semiconductor wafer...
US-9,490,127 Method for manufacturing semiconductor device
A method includes: forming a front surface structure of a semiconductor element on a front surface side of a semiconductor substrate; forming crystal defects in...
US-9,490,126 Resistive memory array using P-I-N diode select device and methods of fabrication thereof
An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such...
US-9,490,125 Methods for forming a molecular dopant monolayer on a substrate
Methods for forming a conformal dopant monolayer on a substrate are provided. In one embodiment, a method for forming a semi-conductor device on a substrate...
US-9,490,124 Polycrystalline silicon substrate and manufacturing method thereof
The present invention discloses a polycrystalline silicon substrate and a manufacturing method thereof. The method comprises: provide a substrate; sequentially...
US-9,490,123 Methods of forming strained epitaxial semiconductor material(S) above a strain-relaxed buffer layer
One illustrative method disclosed herein includes, among other things, sequentially forming a first material layer, a first capping layer, a second material...
US-9,490,122 Method and apparatus of forming carbon-containing silicon film
A method of forming a carbon-containing silicon film includes: adsorbing a silicon source on a workpiece by supplying a silicon source gas containing at least...
US-9,490,121 Plasma-assisted chemical gas separation method having increased plasma density and device for implementing the...
The invention relates to a method and a device for coating surfaces of a substrate (8) according to the technique of plasma-assisted chemical vapor deposition....
US-9,490,120 Vapor transport deposition method and system for material co-deposition
An improved feeder system and method for continuous vapor transport deposition that includes at least two vaporizers couple to a common distributor through an...
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