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Patent # Description
US-9,490,017 Forced-bias method in sub-block erase
A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells includes a plurality of NAND...
US-9,490,016 Semiconductor device and method for fabricating the same
A semiconductor device is disclosed. The semiconductor device includes: a substrate; a floating gate on the substrate; a first silicon oxide layer between the...
US-9,490,015 Semiconductor memory device, memory system having the same, and method of operating the same
A semiconductor memory device, a memory system having the same, and a method of operating the same are provided. The semiconductor memory device includes a...
US-9,490,014 Method and system for accessing a flash memory device
An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory...
US-9,490,013 Semiconductor memory device and method of operating the same
The semiconductor memory device includes a memory cell array including guarantee blocks, normal blocks, and redundancy blocks. A bad block address indicates...
US-9,490,012 Semiconductor memory having both volatile and non-volatile functionality including resistance change material...
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein...
US-9,490,011 Storage device write pulse control
According to an example, a method for storage device write pulse control may include writing a storage device to a first polarity by driving a row address line...
US-9,490,010 Non-volatile memory based synchronous logic
A method for setting resistance states of a first and a second resistive memory element (RME) is disclosed. The method may include coupling, via a common node,...
US-9,490,009 Fast read speed memory device
A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a...
US-9,490,008 9T, 8T, and 7T Bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read...
The present patent application describes 9T, 8T, and 7T versions of bitcells used with 1R1W memories. It also describes 9T, 8T, and 7T versions of bitcells used...
US-9,490,007 Device comprising a plurality of FDSOI static random-access memory bitcells and method of operation thereof
A device including a plurality of static random-access memory (SRAM) bitcells arranged in rows and columns, wherein the SRAM bitcells comprise fully depleted...
US-9,490,006 Time division multiplexed multiport memory
In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has...
US-9,490,005 Memory circuit and method for routing the memory circuit
A memory circuit includes a first row of memory cells, a first word line and a second word line over and electrically coupled to the first row of memory cells,...
US-9,490,004 Semiconductor memory device controlling refresh cycle, memory system, and method of operating the semiconductor...
A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array...
US-9,490,003 Induced thermal gradients
A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from...
US-9,490,002 Reduced refresh power
N out of every M number of refresh commands are ignored (filtered out) by a buffer chip on a memory module. N and M are programmable. The buffer receives...
US-9,490,001 Semiconductor memory device that controls refresh period, memory system and operating method thereof
A semiconductor memory device includes a cell array and a refresh controller coupled to the cell array. The refresh controller is configured to insert at least...
US-9,490,000 Method and system for providing thermally assisted magnetic junctions having a multi-phase operation
A magnetic junction usable in magnetic devices is described. The magnetic junction includes at least one reference layer, at least one nonmagnetic spacer layer...
US-9,489,999 Magnetic tunnel junction resistance comparison based physical unclonable function
A method includes coupling a first magnetic tunnel junction (MTJ) element and a second MTJ element to a comparison circuit. The method also includes comparing,...
US-9,489,998 Magnetic junctions having a magnetoelastic free layer programmable using spin transfer torque
A magnetic junction and method and programming the magnetic junction are described. The magnetic junction has a free layer, a reference layer, and a nonmagnetic...
US-9,489,997 Hardware assisted meta data lookup
A memory system including a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area...
US-9,489,996 Data processing apparatus and method
A data processing apparatus includes a controller configured to provide, using a unified connector, group data processing information for a processing operation...
US-9,489,995 Memory device for realizing sector erase function and operating method thereof
A memory device comprises a plurality of sectors and a driving circuit comprising a global word line driver and a first local word line driver. The global word...
US-9,489,994 Memory timing circuit
A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense...
US-9,489,993 Semiconductor memory apparatus optimized for setting operation parameter and operating parameter setting method...
A semiconductor memory apparatus may include: a memory area; and a controller including a register configured to store parameter setting data, and to provide...
US-9,489,992 Semiconductor device and semiconductor system including the same
A semiconductor device includes a pipe latch suitable for sequentially latching data in response to a pipe input control signal and sequentially outputting data...
US-9,489,991 Memory reading circuit, memory device and method of operating memory device
A circuit for reading a memory device includes a sense amplifier (SA) and a controller. The SA has an input, an output and an enabling terminal. The controller...
US-9,489,990 Adaptive non-volatile memory programming
In an embodiment, a method of programming non-volatile memory (NVM) comprises: determining, by control logic of an NVM system, a number of unsuccessful attempts...
US-9,489,989 Voltage regulators, memory circuits, and operating methods thereof
A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor...
US-9,489,988 Memory device
To provide a memory device where multiple pieces of multilevel data can be written and read. The memory device includes first to fifth transistors, first to...
US-9,489,987 Manufacturing process for a disk drive aperture channel
A method for reducing particulates within a disk drive may comprise providing a first component of a disk drive that is to be coupled to a second component of...
US-9,489,986 Use of program-schedule text and teleprompter output to facilitate selection of a portion of a media-program...
In one aspect, an example method involves accessing first data representing a program schedule of a media program; making a determination that first text of the...
US-9,489,985 Multimedia player displaying operation panel depending on contents
A digital content operating apparatus, including: a communication unit which communicates with an external device which has a display for displaying the digital...
US-9,489,984 Display apparatus, information terminal, display system, and program
A display apparatus which can communicate with an information terminal via a network is disclosed. The display apparatus includes a receiving unit which...
US-9,489,983 Low bandwidth consumption online content editing
Various embodiments of the invention provide systems and methods for low bandwidth consumption online content editing, where user-created content comprising...
US-9,489,982 Television receiver storage management
Various arrangements are presented that may involve receiving from a television service provider, timers that are used to record a managed channel array. Each...
US-9,489,981 Successive initialization of television channel recording
In various arrangements, a television receiver system for successive initialization of television channel recording is presented. The system may include a...
US-9,489,980 Video/audio synchronization apparatus and video/audio synchronization method
A video/audio synchronization apparatus includes: a decoder configured to decode a frame contained in encoded video data and determine playback time of the...
US-9,489,979 Image processing apparatus for time-lapse moving image, image processing method, and storage medium
An image capture apparatus includes a photographic scene selection section and a parameter setting section. The photographic scene selection section selects a...
US-9,489,978 Method of surface-treating metal component
Provided is a method for surface-treating a metal component, whereby a pseudo-plated layer can be formed on a surface of a metal component, and quality...
US-9,489,977 Storage device, controller, and recording and reproducing method
According to one embodiment, there is provided a storage device including a data converter, a recording medium, and an equalizer. The data converter converts...
US-9,489,976 Noise prediction detector adaptation in transformed space
Technologies are described herein for adapting channel parameters of a read channel in a transformed space. A set of channel parameter values associated with...
US-9,489,975 Optical disk device and optical disk processing system having optical disk device
An optical disk device which quickly detects that a transparent disk is loaded is provided. When an optical disk is loaded, a drive controller of an optical...
US-9,489,974 Method of fabricating a BPM template using hierarchical BCP density patterns
The embodiments disclose a method including patterning a template substrate to have different densities using hierarchical block copolymer density patterns in...
US-9,489,973 Magnetic data storage using induced strain of a magnetostrictive material
Acoustically assisted magnetic recording can be used in a hard disk drive or a solid state medium. In the described embodiments, otherwise unwriteable...
US-9,489,972 Light source unit, heat-assisted magnetic recording head using the same, and light source for light source unit
A light source unit has a substrate, a light source that is mounted to the substrate. The light source includes; a first emission part that emits a forward...
US-9,489,971 Flexible circuit for concurrently active recording heads
A system includes a first preamplifier, a second preamplifier and a flex circuit. The first preamplifier is configured to be connected to a first plurality of...
US-9,489,970 Magnetic head and magnetic recording and reproducing apparatus
A magnetic head of an embodiment includes a stack, side shields, and a first and a second magnetic shield. The stack includes a pin layer having a fixed...
US-9,489,969 Magnetic head including a main pole and a write shield to provide improved write characteristics without...
A magnetic head includes a main pole, a write shield and a gap section. The write shield includes a leading shield having a top surface opposed to a bottom end...
US-9,489,968 Thermally-assisted magnetic recording head
A thermally-assisted magnetic recording head of the present invention includes: a stacked-layer structure including a first yoke, a second yoke, a first coil, a...
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