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Patent # Description
US-9,496,391 Termination region of a semiconductor device
In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth...
US-9,496,390 Vertical transistor device with halo pocket contacting source
A vertical transistor device comprises a substrate, a first source, a drain, a first gate dielectric layer, a first gate electrode and a first doping region....
US-9,496,389 Semiconductor devices and methods of manufacturing the same
A semiconductor device includes at least one gate electrode on a substrate structure, at least one drain region doped with impurities of a first conductivity...
US-9,496,388 Trench MOSFET having reduced gate charge
A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the...
US-9,496,387 Semiconductor device, and method for manufacturing the same
A semiconductor device (A1) includes a semiconductor layer having a first face with a trench (3) formed thereon and a second face opposite to the first face, a...
US-9,496,386 Device architecture and method for improved packing of vertical field effect devices
A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or...
US-9,496,385 Structure and method of forming semiconductor device
The present disclosure provides a method for fabricating semiconductor device. The method includes forming a first dielectric layer over a substrate, forming a...
US-9,496,384 Semiconductor device
The present invention provides a semiconductor device that can achieve both low on-resistance and high withstand voltage, while reducing the device size,...
US-9,496,383 Semiconductor device and method of forming the same
A semiconductor device may include, but is not limited to, a semiconductor substrate having a first gate groove; a first fin structure underneath the first gate...
US-9,496,382 Field effect transistor, termination structure and associated method for manufacturing
The present disclosure discloses a field effect transistor ("FET"), a termination structure and associated method for manufacturing. The termination structure...
US-9,496,381 Semiconductor device and method of fabricating the same
A semiconductor device may include a substrate including an active pattern delimited by a device isolation pattern, a gate electrode crossing the active...
US-9,496,380 Compound semiconductor device comprising compound semiconductor layered structure having buffer layer and...
At least one kind of impurity selected from, for example, Fe, C, B, Ti, Cr is introduced into at least a buffer layer of a compound semiconductor layered...
US-9,496,379 Method and structure for III-V FinFET
A method for fabricating a semiconductor device comprises forming a fin in a layer of III-V compound semiconductor material on a silicon-on-insulator substrate;...
US-9,496,378 IGBT with buried emitter electrode
There are disclosed herein various implementations of an insulated gate bipolar transistor (IGBT) with buried emitter electrodes. Such an IGBT may include a...
US-9,496,377 Self-aligned emitter-base-collector bipolar junction transistors with a single crystal raised extrinsic base
Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate,...
US-9,496,376 Method for manufacturing semiconductor device
To provide a semiconductor device with improved reliability. To provide a semiconductor device with stable characteristics. To provide a transistor having a low...
US-9,496,375 Method for manufacturing semiconductor device
To improve productivity of a transistor that includes an oxide semiconductor and has good electrical characteristics. In a top-gate transistor including a gate...
US-9,496,374 Method for manufacturing thin-film transistor substrate
The present invention provides a method for manufacturing a thin-film transistor substrate, which has a simple process and achieves an excellent contact...
US-9,496,373 Damage-resistant fin structures and FinFET CMOS
A design structure for a semiconductor circuit structure, readable by a machine used in design, manufacture, or simulation of an integrated circuit, involves a...
US-9,496,372 Method of making a FinFET device
A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming first and second gate stacks over first and...
US-9,496,371 Channel protection during fin fabrication
A method for protecting channels during fin fabrication. Fins are formed on a substrate. A conformal liner layer (or layers) is applied on the fins. Active...
US-9,496,370 Manufacturing method of semiconductor apparatus and semiconductor apparatus
A screen oxide film is formed on an n- drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed...
US-9,496,369 Method of forming split-gate memory cell array along with low and high voltage logic devices
A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area,...
US-9,496,368 Partial spacer for increasing self aligned contact process margins
A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on...
US-9,496,367 Mechanism for forming metal gate structure
A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer...
US-9,496,366 Method for manufacturing silicon carbide (SiC) semiconductor device by introducing nitrogen concentration of...
A method for manufacturing a semiconductor device includes forming a thermal oxide film on one surface of an SiC substrate by thermal oxidation at a temperature...
US-9,496,365 Semiconductor device and manufacturing method for the same
A semiconductor device of an embodiment includes: an SiC layer; a gate insulating film provided on a surface of the SiC layer, the gate insulating film...
US-9,496,364 Field effect semiconductor component and methods for operating and producing it
In accordance with one component, a power field effect transistor is proposed, including a substrate, a channel, a gate electrode, and a gate insulator. The...
US-9,496,363 FinFET isolation structure and method for fabricating the same
A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin...
US-9,496,362 Contact first replacement metal gate
A technique relates to forming a semiconductor device. Sacrificial gates are formed on a channel region of a substrate. Epitaxial layers are grown on...
US-9,496,361 Selectively deposited metal gates and method of manufacturing thereof
A manufacturing method of a semiconductor structure includes the following steps. Gate trenches are formed in a first dielectric layer on a semiconductor...
US-9,496,360 Vertical transistor with source/drain regions induced by work-function differences between a semiconductor...
A semiconductor device includes a pillar-shaped semiconductor having an impurity concentration of 10.sup.17 cm.sup.-3 or less. A first insulator surrounds the...
US-9,496,359 Integrated circuit having chemically modified spacer surface
A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack...
US-9,496,358 Semiconductor device and fabrication method therefor
A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate...
US-9,496,357 Semiconductor device
A trench MOSFET including: an epitaxial layer; a body region on the epitaxial layer, the body region and the epitaxial layer forming a first interface; a...
US-9,496,356 Under-spacer doping in fin-based semiconductor devices
A fin field effect transistor (FinFET) device and a method of fabricating the FinFET are described. The device includes a fin formed on a substrate, the fin...
US-9,496,355 Conductive nanoparticles
Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in...
US-9,496,354 Semiconductor devices with dummy gate structures partially on isolation regions
One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a...
US-9,496,353 Fabrication of single or multiple gate field plates
A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and...
US-9,496,352 Semiconductor device
According to one embodiment, a semiconductor device includes: a first semiconductor region; a second semiconductor region on the first semiconductor region; a...
US-9,496,351 Semiconductor chip arrangement
A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a...
US-9,496,350 P-type ZnO based compound semiconductor layer, a ZnO based compound semiconductor element, and an N-type ZnO...
A p-type ZnO based compound semiconductor single crystal layer, wherein the layer includes a p-type ZnO based compound semiconductor single crystal layer...
US-9,496,349 P-doping of group-III-nitride buffer layer structure on a heterosubstrate
An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management...
US-9,496,348 Method for doping a GaN-base semiconductor
The method for doping a GaN-base semiconductor to fabricate a p-n junction includes a first step consisting in providing a substrate including a GaN-base...
US-9,496,347 Graded buffer epitaxy in aspect ratio trapping
A method of forming a semiconductor device includes: providing a patterned structure comprising a silicon substrate and dielectric stacks deposited on the...
US-9,496,346 Silicon carbide device and a method for forming a silicon carbide device
A silicon carbide device includes a silicon carbide substrate, an inorganic passivation layer structure and a molding material layer. The inorganic passivation...
US-9,496,345 Semiconductor structure, semiconductor device, and method for producing semiconductor structure
The present invention provides a semiconductor structure which includes at least a p-type silicon carbide single crystal layer having an .alpha.-type crystal...
US-9,496,344 Semiconductor device including well regions with different impurity densities
In a JBS diode using a wide band gap semiconductor, the wide band gap semiconductor has a large built-in voltage, which sometimes causes difficulties for the pn...
US-9,496,343 Secondary use of aspect ratio trapping holes as eDRAM structure
A semiconductor structure is provided according to a method in which an aspect ratio trapping process is employed. The structure includes a semiconductor...
US-9,496,342 MOSFET structure and manufacturing method thereof
A MOSFET and a method for manufacturing the same are disclosed. The method comprises: a. providing a substrate (100), a dummy gate structure (200), a epitaxial...
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